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PDF M29W008AT Data sheet ( Hoja de datos )
| Número de pieza | M29W008AT | |
| Descripción | 8 Mbit 1Mb x8 / Boot Block Low Voltage Single Supply Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M29W008AT
M29W008AB
8 Mbit (1Mb x8, Boot Block)
Low Voltage Single Supply Flash Memory
s 2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
s ACCESS TIME: 80ns
s PROGRAMMING TIME: 10µs typical
s PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
s SECURITY PROTECTION MEMORY AREA
s INSTRUCTIONS ADDRESS CODING: 3 digits
s MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
s BLOCK, MULTI-BLOCK and CHIP ERASE
s MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M29W008AT: D2h
– Bottom Device Code, M29W008AB: DCh
TSOP40 (N)
10 x 20mm
Figure 1. Logic Diagram
VCC
20
A0-A19
8
DQ0-DQ7
W
M29W008AT
E M29W008AB RB
G
RP
VSS
AI02716
March 2000
1/30
1 page  
M29W008AT, M29W008AB
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs
for the memory array are latched during a write op-
eration on the falling edge of Chip Enable E or
Write Enable W. When A9 is raised to VID, either a
Read Electronic Signature Manufacturer or Device
Code, Block Protection Status or a Write Block
Protection or Block Unprotection is enabled de-
pending on the combination of levels on A0, A1
A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is
data to be programmed in the memory array or a
command to be written to the C.I. Both are latched
on the rising edge of Chip Enable E or Write En-
able W. The output is data from the Memory Array,
the Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high im-
pedance when the chip is deselected or the out-
puts are disabled and when RP is at a Low level.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E High deselects the
memory and reduces the power consumption to
the stand-by level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at a low level. The Chip
Enable must be forced to VID during the Block Un-
protection operation.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is High the outputs are High im-
pedance. G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output and gives the internal state of
the P/E.C. of the device. When RB is Low, the de-
vice is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend in-
struction.
When RB is High, the device is ready for any
Read, Program or Erase operation. The RB will
also be High when the memory is put in Erase
Suspend or Stand-by modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is achieved by pulling RP to
VIL for at least tPLPX. When the reset pulse is giv-
en, if the memory is in Read or Stand-by modes, it
will be available for new operations in tPHEL after
the rising edge of RP.
If the memory is in Erase, Erase Suspend or Pro-
gram modes the reset will take tPLYH during which
the RB signal will be held at VIL. The end of the
memory reset will be indicated by the rising edge
of RB. A hardware reset during an Erase or Pro-
gram operation will corrupt the data being pro-
grammed or the sector(s) being erased. See
Tables 15, 16 and Figure 8.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RP from VIH to VID must slower than tPH-
PHH. (See Tables 17, 18 and Figure 8). When RP
is returned from VID to VIH all blocks temporarily
unprotected will be again protected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
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5 Page 
M29W008AT, M29W008AB
Table 11. Polling and Toggle Bits
Mode
DQ7 DQ6 DQ2
Program
DQ7 Toggle 1
Erase
0 Toggle Note 1
Erase Suspend Read
(in Erase Suspend
1 1 Toggle
block)
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program DQ7 Toggle N/A
Note: 1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to '1' during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to '1' dur-
ing program operation and when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to '1', DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block
erase or program, the block in which the error oc-
curred or to which the programmed data belongs,
must be discarded. The DQ5 failure condition will
also appear if a user tries to program a '1' to a lo-
cation that is previously programmed to '0'. Other
Blocks may still be used. The error bit resets after
a Read/Reset (RD) instruction. In case of success
of Program or Erase, the error bit will be set to '0'.
Erase Timer Bit (DQ3). This bit is set to '0' by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 90µs, DQ3 returns
to '1'.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address 555h during the
first cycle. During the second cycle the Coded cy-
cles consist of writing the data 55h at address
2AAh. A0 to A11 are valid, other address lines are
’don’t care’. The Coded cycles happen on first and
second cycles of the command write or on the
fourth and fifth cycles.
Instructions
See Table 9.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. A wait state of 10µs is nec-
essary after Read/Reset prior to any valid read if
the memory was in an Erase mode when the RD
instruction is given. The Read/Reset command is
not accepted during Erase and Erase Suspend.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the manufacturer code and the device code or the
block protection status depending on the levels of
A0 and A1. The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code, EAh for Top Boot, EBh for Bottom
Boot is output when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the AS instruction,
A0 and A6 are set to VIL with A1 at VIH, while A13-
A19 define the address of the block to be verified.
A read in these conditions will output a 01h if the
block is protected and a 00h if the block is not pro-
tected.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the P/
E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing '0' in place of
'1'. Status bits DQ6 and DQ7 determine if pro-
gramming is on-going and DQ5 allows verification
of any possible error. Programming at an address
not in blocks being erased is also possible during
erase suspend. In this case, DQ2 will toggle at the
address being programmed.
11/30
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