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PDF M29W004B Data sheet ( Hoja de datos )

Número de pieza M29W004B
Descripción 4 Mbit 512Kb x8 / Boot Block Low Voltage Single Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M29W004B Hoja de datos, Descripción, Manual

M29W004T
M29W004B
4 Mbit (512Kb x8, Boot Block)
Low Voltage Single Supply Flash Memory
M29W004T and M29W004B are replaced
respectively by the M29W004BT and
M29W004BB
2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29W004T: EAh
– Device Code, M29W004B: EBh
DESCRIPTION
The M29W004 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V VCC supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
NOT FOR NEW DESIGN
TSOP40 (N)
10 x 20 mm
Figure 1. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W
M29W004T
E M29W004B RB
G
RP
VSS
AI02063
June 1999
This is information on a product still in production but not recommended for new designs.
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M29W004B pdf
M29W004T, M29W004B
Table 3A. M29W004T Block Address Table
Address Range
A18 A17 A16 A15 A14 A13
00000h-0FFFFh
0 0 0XXX
10000h-1FFFFh
0 0 1XXX
20000h-2FFFFh
0 1 0XXX
30000h-3FFFFh
0 1 1XXX
40000h-4FFFFh
1 0 0XXX
50000h-5FFFFh
1 0 1XXX
60000h-6FFFFh
1 1 0XXX
70000h-77FFFh
1 1 1 0XX
78000h-79FFFh
111100
7A000h-7BFFFh
111101
7C000h-7FFFFh
11111X
Table 3B. M29W004B Block Address Table
Address Range
A18 A17 A16 A15 A14 A13
00000h-03FFFh
00000X
04000h-05FFFh
000010
06000h-07FFFh
000011
08000h-0FFFFh
0 0 0 1XX
10000h-1FFFFh
0 0 1XXX
20000h-2FFFFh
0 1 0XXX
30000h-3FFFFh
0 1 1XXX
40000h-4FFFFh
1 0 0XXX
50000h-5FFFFh
1 0 1XXX
60000h-6FFFFh
1 1 0XXX
70000h-7FFFFh
1 1 1XXX
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M29W004B arduino
M29W004T, M29W004B
Table 10. Polling and Toggle Bits
Mode
DQ7 DQ6 DQ2
Program
Erase
DQ7
0
Toggle 1
Toggle Note 1
Erase Suspend Read
(in Erase Suspend
block)
1 1 Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program DQ7 Toggle N/A
Note: 1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operation and when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block erase
or program, the block in which the error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pear if a user tries to program a ’1’ to a location that
is previously programmed to ’0’. Other Blocks may
still be used. The error bit resets after a Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 90µs, DQ3 returns
to ’1’.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address 5555h during the
first cycle. During the second cycle the Coded
cycles consist of writing the data 55h at address
2AAAh. A0 to A14 are valid, other address lines are
’don’t care’. The Coded cycles happen on first and
second cycles of the command write or on the
fourth and fifth cycles.
Instructions
See Table 8.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by the
two Coded cycles. Subsequent read operations will
read the memory array addressed and output the
data read. A wait state of 10µs is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 5555h
for command set-up. A subsequent read will output
the manufacturer code and the device code or the
block protection status depending on the levels of
A0 and A1 The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code, EAh for Top Boot, EBh for Bottom
Boot is output when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the AS instruction, A0
and A6 are set to VIL with A1 at VIH, while A13-A18
define the address of the block to be verified. A read
in these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 5555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if program-
ming is on-going and DQ5 allows verification of any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dress being programmed.
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