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PDF M29W004 Data sheet ( Hoja de datos )

Número de pieza M29W004
Descripción 4 Mbit 512Kb x8 / Boot Block Low Voltage Single Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M29W004 Hoja de datos, Descripción, Manual

M29W004BT
M29W004BB
4 Mbit (512Kb x8, Boot Block)
Low Voltage Single Supply Flash Memory
s SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
s ACCESS TIME: 55ns
s PROGRAMMING TIME
– 10µs by Byte typical
s 11 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 8 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s TEMPORARY BLOCK UNPROTECTION
MODE
s UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
s LOW POWER CONSUMPTION
– Standby and Automatic Standby
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code M29W004BT: EAh
– Bottom Device Code M29W004BB: EBh
TSOP40 (N)
10 x 20mm
Figure 1. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W
M29W004BT
E M29W004BB RB
G
RP
VSS
AI02954
March 2000
1/20

1 page




M29W004 pdf
M29W004BT, M29W004BB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 5, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 7, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 8 and 9, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 5, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against acci-
dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.
Table 5. Bus Operations
Operation
E GW
Address Inputs
Data
Inputs/Outputs
Bus Read
VIL VIL VIH Cell Address
Data Output
Bus Write
VIL VIH VIL Command Address
Data Input
Output Disable
X VIH VIH X
Hi-Z
Standby
VIH X
XX
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
20h
Read Device Code
Note: X = VIL or VIH.
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
EAh (M29W004BT)
EBh (M29W004BB)
5/20

5 Page





M29W004 arduino
Table 9. AC Measurement Conditions
Parameter
VCC Supply Voltage
Load Capacitance (CL)
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
55
3.0 to 3.6V
30pF
10ns
0 to 3V
1.5V
M29W004BT, M29W004BB
M29W004B
70
2.7 to 3.6V
30pF
10ns
0 to 3V
1.5V
90 / 120
2.7 to 3.6V
100pF
10ns
0 to 3V
1.5V
Figure 5. AC Testing Input Output Waveform
3V
1.5V
0V
AI01417
Figure 6. AC Testing Load Circuit
0.8V
1N914
DEVICE
UNDER
TEST
3.3k
OUT
CL = 30pF or 100pF
Table 10. Capacitance
(TA = 25 °C, f = 1 MHz)
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
Note: Sampled only, not 100% tested.
CL includes JIG capacitance
AI02762
Test Condition
VIN = 0V
VOUT = 0V
Min Max Unit
6 pF
12 pF
11/20

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