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PDF M29F100BB Data sheet ( Hoja de datos )

Número de pieza M29F100BB
Descripción 1 Mbit 128Kb x8 or 64Kb x16 / Boot Block Single Supply Flash Memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M29F100BT
M29F100BB
1 Mbit (128Kb x8 or 64Kb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA
s SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
s ACCESS TIME: 45ns
s PROGRAMMING TIME
– 8µs per Byte/Word typical
s 5 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 2 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
s TEMPORARY BLOCK UNPROTECTION
MODE
s LOW POWER CONSUMPTION
– Standby and Automatic Standby
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– M29F100BT Device Code: 00D0h
– M29F100BB Device Code: 00D1h
44
TSOP48 (N)
12 x 20mm
1
SO44 (M)
Figure 1. Logic Diagram
VCC
16
A0-A15
15
DQ0-DQ14
W DQ15A–1
M29F100BT
E M29F100BB BYTE
G RB
RP
VSS
AI02916
July 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M29F100BB pdf
M29F100BT, M29F100BB
Table 4A. Bus Operations, BYTE = VIL
Operation
E GW
Bus Read
VIL VIL VIH
Bus Write
VIL VIH VIL
Output Disable
X VIH VIH
Standby
VIH X
X
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code VIL VIL VIH
Note: X = VIL or VIH.
Address Inputs
DQ15A–1, A0-A15
Data Inputs/Outpu ts
DQ14-DQ8
DQ7-DQ0
Cell Address
Hi-Z Data Output
Command Address
Hi-Z Data Input
X Hi-Z Hi-Z
X Hi-Z Hi-Z
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
20h
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
D0h (M29F100BT)
D1h (M29F100BB)
Table 4B. Bus Operations, BYTE = VIH
Operation
E GW
Bus Read
VIL VIL VIH
Bus Write
VIL VIH VIL
Output Disable
X VIH VIH
Standby
VIH X
X
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code VIL VIL VIH
Note: X = VIL or VIH.
Address Inputs
A0-A15
Cell Address
Command Address
X
X
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Data Inputs/Outpu ts
DQ15A–1, DQ14-DQ0
Data Output
Data Input
Hi-Z
Hi-Z
0020h
00D0h (M29F100BT)
00D1h (M29F100BB)
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 4A and 4B, Bus Operations, for a summa-
ry. Typically glitches of less than 5ns on Chip En-
able or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 7, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 8 and 9, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
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M29F100BB arduino
Figure 3. Data Polling Flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
NO DQ5
=1
YES
READ DQ7
DQ7
=
YES
DATA
NO
FAIL
PASS
AI01369
M29F100BT, M29F100BB
Figure 4. Data Toggle Flowchart
START
READ
DQ5 & DQ6
DQ= 6
NO
TOGGLE
YES
NO DQ5
=1
YES
READ DQ6
DQ= 6
NO
TOGGLE
YES
FAIL
PASS
AI01370
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
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