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PDF M29F002NT Data sheet ( Hoja de datos )
| Número de pieza | M29F002NT | |
| Descripción | 2 Mbit 256Kb x8 / Boot Block Single Supply Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M29F002T, M29F002NT
M29F002B
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
5V ± 10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29F002T: B0h
– Device Code, M29F002NT: B0h
– Device Code, M29F002B: 34h
DESCRIPTION
The M29F002 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single5V VCC supply.For Program and
Erase operations the necessary high voltages are
generated internally. The device can also be pro-
grammed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
July 1998
32
1
PDIP32 (P)
PLCC32 (K)
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
VCC
18
A0-A17
8
DQ0-DQ7
W
E
G
(*) RPNC
M29F002T
M29F002B
M29F002NT
VSS
AI02078C
Note: * RPNC function is not available for the M29F002NT
1/29
1 page  
M29F002T, M29F002NT, M29F002B
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the ElectronicSignature
or Block ProtectionStatus), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations.The Status Register Data Polling, Tog-
gle, Error bits may be read at any time, during
programming or erase, to monitor the progress of
the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interfacewhich iscommon to all instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection,the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Programinstruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended,in orderto read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if VCC falls below
VLKO, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A17). The address inputs for
the memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to VID, either a Read
ElectronicSignature Manufactureror Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is data
to be programmed in the memory array or a com-
mand to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputs are disabled and when RPNC is at a Low
level.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselectsthe memory
and reduces the power consumptionto the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to VID during the Block Unprotection opera-
tion.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to the
Command Registerand Addressand Datalatches.
Reset/Block Temporary Unprotect/No Connect
Input (RPNC). The RPNC (not available for the
M29F002NT) input provides hardware reset and
protected block(s) temporary unprotection func-
tions. In read or write mode, the RPNC pin can be
left open (Not Connected) or held at VIH. Reset of
the memory is acheived by pulling RPNC to VIL for
at least 500ns. When the reset pulse is given, if the
memory is in Read or Standby modes, it will be
available for new operations in 50ns after the rising
edge of RPNC. If the memory is in Erase, Erase
Suspend or Program modes the reset will take
10µs. Ahardware reset duringan Eraseor Program
operation will corrupt the data being programmed
or the sector(s) being erased.
Temporary block unprotection is made by holding
RPNC at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RPNC from VIH to VID must slower than
500ns. When RPNC is returned from VID to VIH all
blocks temporarily unprotected will be again pro-
tected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
DEVICE OPERATIONS
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
5/29
5 Page 
Table 11. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
M29F002T, M29F002NT, M29F002B
High Speed
≤ 10ns
0 to 3V
1.5V
Standard
≤ 10ns
0.45V to 2.4V
0.8V and 2V
Figure 4. AC Testing Input Output Waveform
High Speed
3V
0V
Standard
2.4V
0.45V
1.5V
2.0V
0.8V
AI01275B
Figure 5. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
CL
OUT
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01276B
Table 12. Capacitance(1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
CIN Input Capacitance
VIN = 0V
C OUT
Output Capacitance
Note: 1. Sampled only, not 100% tested.
VOUT = 0V
Min Max Unit
6 pF
12 pF
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. Asubsequentread will output the
manufacturer code and the device code or the
block protection status depending on the levels of
A0 and A1. The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code is output when A0 is High with A1 Low.
The AS instruction also allows access to the block
protectionstatus. After givingthe AS instruction, A0
is set to VIL with A1 at VIH, while A13-A17 define
the address of the block to be verified. A read in
these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if program-
ming is on-goingand DQ5 allows verification of any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dress being programmed.
11/29
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| PDF Descargar | [ Datasheet M29F002NT.PDF ] | |
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