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PDF M29F002 Data sheet ( Hoja de datos )

Número de pieza M29F002
Descripción 2M-BIT [256K x 8] CMOS FLASH MEMORY
Fabricantes Macronix International 
Logotipo Macronix International Logotipo



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MX29F002/002N
2M-BIT [256K x 8] CMOS FLASH MEMORY
FEATURES
• 262,144x 8 only
• Fast access time: 55/70/90/120ns
• Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
• Programming and erasing voltage 5V ± 10%
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte
x1, and 64K-Byte x 3)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or the
whole chip with Erase Suspend capability.
- Automatically programs and verifies data at specified
address
• Erase Suspend/Erase Resume
- Suspends an erase operation to read data from, or
program data to, a sector that is not being erased, then
resumes the erase operation.
• Status Reply
- Data polling & Toggle bit for detection of program and
erase cycle completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/
12V system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Hardware RESET pin(only for 29F002T/B)
- Resets internal state machine to read mode
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
• 20 years data retention
GENERAL DESCRIPTION
The MX29F002T/B is a 2-mega bit Flash memory organ-
ized as 256K bytes of 8 bits only. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29F002T/B is
packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is
designed to be reprogrammed and erased in-system or in-
standard EPROM programmers.
The standard MX29F002T/B offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F002T/B has separate chip enable (CE) and output
enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F002T/B uses a command register to manage this
functionality. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
MXIC's Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F002T/B uses a 5.0V ± 10% VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved with
MXIC's proprietary non-epi process. Latch-up protection
is proved for stresses up to 100 milliamps on address and
data pin from -1V to VCC + 1V.
P/N: PM0547
1 REV. 1.1, JUN. 14, 2001

1 page




M29F002 pdf
MX29F002/002N
TABLE1. SOFTWARE COMMAND DEFINITIONS
Command
Reset
Read
Read Silicon ID
Sector Protect
Verification
Porgram
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Unlock for sector
protect/unprotect
First Bus
Bus Cycle
Cycle Addr Data
Second Bus
Cycle
Addr Data
1 XXXH F0H
1 RA RD
4 555H AAH 2AAH 55H
4 555H AAH 2AAH 55H
4 555H AAH 2AAH 55H
6 555H AAH 2AAH 55H
6 555H AAH 2AAH 55H
1 XXXH B0H
1 XXXH 30H
6 555H AAH 2AAH 55H
Third Bus
Cycle
Addr Data
Fourth Bus
Cycle
Addr Data
Fifth Bus
Cycle
Sixth Bus
Cycle
Addr Data Addr Data
555H 90H ADI DDI
555H 90H (SA) 00H
(X02H) 01H
555H A0H PA PD
555H 80H 555H AAH 2AAH 55H 555H 10H
555H 80H 555H AAH 2AAH 55H SA 30H
555H 80H 555H AAH 2AAH 55H 555H 20H
Note:
1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3).
DDI = Data of Device identifier : C2H for manufacture code, 00B0h/0034h for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't
care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated
with A11~A17 in either state.
4.For Sector Protect Verification Operation : If read out data is 01H, it means the sector has been protected. If read out data is 00H,
it means the sector is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the read
mode. Table 1 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset command sequences will reset the device(when
applicable).
P/N: PM0547
REV. 1.1, JUN. 14, 2001
5

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M29F002 arduino
MX29F002/002N
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is, the
Automatic Erase alorithm is in process), or whether that
sector is erase-suspended. Toggle Bit I is valid after the
rising edge of the final WE pulse in the command sequence.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. Q6, by comparison,
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required
for sectors and mode information. Refer to Table 4 to
compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Refer to the toggle bit algorithm for the following discussion.
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the first.
If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read
array data on Q7-Q0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of Q5 is high (see the
section on Q5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as Q5 went high. If the
toggle bit is no longer toggling, the device has successfuly
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset command
to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and Q5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when
it returns to determine the status of the operation(top of the
toggle bit algorithm flow chart).
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
which indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence.
This allows the system to continue to use the other active
sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire sector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
reused).
The Q5 time-out condition may also appear if a user tries
to program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.
P/N: PM0547
REV. 1.1, JUN. 14, 2001
11

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