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PDF MC14020 Data sheet ( Hoja de datos )

Número de pieza MC14020
Descripción 14-Bit Binary Counter
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No Preview Available ! MC14020 Hoja de datos, Descripción, Manual

MC14020B
14-Bit Binary Counter
The MC14020B 14–stage binary counter is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripple–carry binary counter. The device
advances the count on the negative–going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency–dividing circuits.
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Buffered Outputs Available from stages 1 and 4 thru 14
Common Reset Line
Pin–for–Pin Replacement for CD4020B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note NO TAG)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation,
500 mW
per Package (Note NO TAG)
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14020BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14020B
AWLYWW
1
TSSOP–16
DT SUFFIX
CASE 948F
16
14
020B
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14020B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14020BCP
PDIP–16
2000/Box
MC14020BD
SOIC–16
48/Rail
MC14020BDR2 SOIC–16 2500/Tape & Reel
MC14020BDT
TSSOP–16
96/Rail
MC14020BF
SOEIAJ–16 See Note 1.
MC14020BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14020B/D

1 page




MC14020 pdf
MC14020B
500 µF
VDD
ID
0.01 µF
CERAMIC
PULSE
GENERATOR
C Q1
Q4
R Qn
VSS
CL
CL
CL
CLOCK
20 ns
90%
50%
10%
50% DUTY CYCLE
20 ns
VDD
VSS
Figure 1. Power Dissipation Test Circuit
and Waveform
PULSE
GENERATOR
VDD
C Q1
Q4
R Qn
VSS
CL
CL
CL
CLOCK
Q
tTLH
20 ns
tPLH
90%
50%
10%
90%
50%
10%
tWH
tTHL
20 ns
tPHL
Figure 2. Switching Time Test Circuit
and Waveforms
CLOCK
RESET
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16,384
Figure 3. Timing Diagram
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