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PDF MC14015BFEL Data sheet ( Hoja de datos )

Número de pieza MC14015BFEL
Descripción Dual 4-Bit Static Shift Register
Fabricantes ON Semiconductor 
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No Preview Available ! MC14015BFEL Hoja de datos, Descripción, Manual

MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4–bit static shift register is constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4–state serial–input/parallel–output registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master–slave flip–flops. Data is shifted
from one stage to the next during the positive–going clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial–to–parallel conversion where low power
dissipation and/or noise immunity is desired.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14015BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14015B
AWLYWW
1
TSSOP–16
DT SUFFIX
CASE 948F
16
14
015B
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14015B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14015BCP
PDIP–16
2000/Box
MC14015BD
SOIC–16
48/Rail
MC14015BDR2 SOIC–16 2500/Tape & Reel
MC14015BDT
TSSOP–16 2000/Tape & Reel
MC14015BF
SOEIAJ–16 See Note 1.
MC14015BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14015B/D

1 page




MC14015BFEL pdf
SYNC
PULSE
GENERATOR
2
PULSE
GENERATOR
1
MC14015B
DATA
INPUT
VDD tTLH
D Q0
Q1
Q2
C Q3
R
CL
CL
CL
CL
CLOCK
INPUT
VSS
Q0
tWL = tWH = 50% Duty Cycle
tTLH = tTHL 20 ns
tTLH
tsu
t–
tWH
tPLH
90%
50%
10%
tTHL
90%
50%
10%
tWL
tPHL
90%
tTHL
VDD
0V
VDD
0V
50%
10%
tTLH tTHL
Figure 2. Switching Test Circuit and Waveforms
SYNC
PULSE
GENERATOR
2
PULSE
GENERATOR
1
VDD
D Q0
Q1
Q2
C Q3
R
CL
CL
CL
CL
VSS
CLOCK
INPUT
DATA
INPUT
50%
tsu
th
50%
VDD
0V
VDD
0V
Figure 3. Setup and Hold Time Test Circuit and Waveforms
http://onsemi.com
5

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MC14015BFEL arduino
16
1
e
Z
D
b
0.13 (0.005) M
MC14015B
PACKAGE DIMENSIONS
9
E HE
8
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
LE
M_
Q1
L
DETAIL P
VIEW P
A
c
A1
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC
0.050 BSC
HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0 _ 10 _ 0 _ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031
http://onsemi.com
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