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PDF MC14012BD Data sheet ( Hoja de datos )

Número de pieza MC14012BD
Descripción B-Suffix Series CMOS Gates
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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MC14012B
B-Suffix Series CMOS Gates
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
http://onsemi.com
PDIP–14
P SUFFIX
CASE 646
MARKING
DIAGRAMS
14
MC14012BCP
AWLYYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
SOIC–14
D SUFFIX
CASE 751A
14
14012B
AWLYWW
1
SOEIAJ–14
F SUFFIX
CASE 965
14
MC14012B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14012BCP
PDIP–14
2000/Box
MC14012BD
SOIC–14
55/Rail
MC14012BDR2 SOIC–14 2500/Tape & Reel
MC14012BF
SOEIAJ–14 See Note 1.
MC14012BFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 3
1
Publication Order Number:
MC14012B/D

1 page




MC14012BD pdf
MC14012B
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR
4.0
SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND
2.0
1.0
0
0 1.0 2.0 3.0 4.0 5.0
Vin, INPUT VOLTAGE (Vdc)
Figure 8. VDD = 5.0 Vdc
SINGLE INPUT NAND, AND
10 MULTIPLE INPUT NOR, OR
8.0
SINGLE INPUT NOR, OR
6.0 MULTIPLE INPUT NAND, AND
4.0
2.0
0
0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc)
Figure 9. VDD = 10 Vdc
16
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR
12
SINGLE INPUT NOR, OR
10 MULTIPLE INPUT NAND, AND
8.0
6.0
4.0
2.0
0
0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc)
Figure 10. VDD = 15 Vdc
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Vout VDD
VO
Vout VDD
VO
VO
0
VO
VDD
Vin 0
VDD
Vin
VIL VIH
(a) Inverting Function
VSS = 0 VOLTS DC
VIL VIH
(b) Non–Inverting Function
Figure 11. DC Noise Immunity
http://onsemi.com
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