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PDF PERICOMPI7C8150 Data sheet ( Hoja de datos )
| Número de pieza | PERICOMPI7C8150 | |
| Descripción | 2-Port PCI-to-PCI Bridge | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI7C8150
2-Port PCI-to-PCI Bridge
REVISION 1.02
2380 Bering Drive, San Jose, CA 95131
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Email: [email protected]
Internet: http://www.pericom.com
1 page  
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
4.3 MEMORY ADDRESS DECODING ........................................................................................... 31
4.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 32
4.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 33
4.4 VGA SUPPORT ........................................................................................................................... 34
4.4.1 VGA MODE ......................................................................................................................... 34
4.4.2 VGA SNOOP MODE........................................................................................................... 34
5 TRANSACTION ORDERING.......................................................................................................... 35
5.1 TRANSACTIONS GOVERNED BY ORDERING RULES ....................................................... 35
5.2 GENERAL ORDERING GUIDELINES ..................................................................................... 36
5.3 ORDERING RULES .................................................................................................................... 36
5.4 DATA SYNCHRONIZATION .................................................................................................... 37
6 ERROR HANDLING......................................................................................................................... 38
6.1 ADDRESS PARITY ERRORS .................................................................................................... 38
6.2 DATA PARITY ERRORS ........................................................................................................... 39
6.2.1 CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 39
6.2.2 READ TRANSACTIONS .................................................................................................... 39
6.2.3 DELAYED WRITE TRANSACTIONS............................................................................... 40
6.2.4 POSTED WRITE TRANSACTIONS.................................................................................. 43
6.3 DATA PARITY ERROR REPORTING SUMMARY................................................................. 44
6.4 SYSTEM ERROR (SERR#) REPORTING ................................................................................. 48
7 EXCLUSIVE ACCESS ...................................................................................................................... 49
7.1 CONCURRENT LOCKS ............................................................................................................. 49
7.2 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150 ....................................................... 49
7.2.1 LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 49
7.2.2 LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 51
7.3 ENDING EXCLUSIVE ACCESS................................................................................................ 51
8 PCI BUS ARBITRATION................................................................................................................. 51
8.1 PRIMARY PCI BUS ARBITRATION ........................................................................................ 52
8.2 SECONDARY PCI BUS ARBITRATION .................................................................................. 52
8.2.1 SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 52
8.2.2 PREEMPTION .................................................................................................................... 54
8.2.3 SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 54
8.2.4 BUS PARKING.................................................................................................................... 54
9 CLOCKS ............................................................................................................................................. 55
9.1 PRIMARY CLOCK INPUTS....................................................................................................... 55
9.2 SECONDARY CLOCK OUTPUTS ............................................................................................ 55
10 GENERAL PURPOSE I/O INTERFACE.................................................................................... 55
10.1 GPIO CONTROL REGISTERS................................................................................................... 55
10.2 SECONDARY CLOCK CONTROL............................................................................................ 56
10.3 LIVE INSERTION ....................................................................................................................... 58
11 PCI POWER MANAGEMENT .................................................................................................... 58
12 RESET ............................................................................................................................................. 59
12.1 PRIMARY INTERFACE RESET ................................................................................................ 59
12.2 SECONDARY INTERFACE RESET.......................................................................................... 59
12.3 CHIP RESET................................................................................................................................ 60
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August 22, 2002 – Revision 1.02
5 Page 
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
1 INTRODUCTION
Product Description
The PI7C8150 is Pericom Semiconductor’s third-generation PCI-PCI Bridge.
It is designed to be fully compliant with the 32-bit, 66MHz implementation of
the PCI Local Bus Specification, Revision 2.2. The PI7C8150 supports only synchronous
bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the
Secondary Buses operating at either 33MHz or 66MHz. The Primary and Secondary Bus
can also operate in concurrent mode, resulting in added increase in system performance.
Concurrent bus operation off-loads and isolates unnecessary traffic from the Primary Bus,
thereby enabling a master and a target device on the Secondary PCI Bus to communicate
even while the Primary Bus is busy.
Product Features
· 32-bit Primary and Secondary Ports run up to 66MHz
· Compliant with the PCI Local Bus Specification, Revision 2.2
· Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1.
- All I/O and memory commands
- Type 1 to Type 0 configuration conversion
- Type 1 to Type 1 configuration forwarding
- Type 1 configuration write to special cycle conversion
· Compliant with the Advanced Configuration Power Interface (ACPI) Specification.
· Compliant with the PCI Power Management Specification, Revision 1.0.
· Concurrent Primary to Secondary Bus operation and independent intra-Secondary Port
channel to reduce traffic on the Primary Port
· Provides internal arbitration for one set of nine secondary bus masters
- Programmable 2-level priority arbiter
- Disable control for use of external arbiter
· Supports posted write buffers in all directions
· Two 128 byte FIFO’s for delay transactions
· Two 128 byte FIFO’s for posted memory transactions
· Enhanced address decoding
- 32-bit I/O address range
- 32-bit memory-mapped I/O address range
- VGA addressing and VGA palette snooping
- ISA-aware mode for legacy support in the first 64KB of I/O address range
· Interrupt handling
- PCI interrupts are routed through an external interrupt concentrator
· Supports system transaction ordering rules
· Extended commercial temperature range 0°C to 85°C
· IEEE 1149.1 JTAG interface support
· 3.3V core; 3.3V and 5V signaling
· 208-pin FQFP package
1
August 22, 2002 – Revision 1.02
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| PDF Descargar | [ Datasheet PERICOMPI7C8150.PDF ] | |
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