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PDF PEF2256 Data sheet ( Hoja de datos )

Número de pieza PEF2256
Descripción E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
Fabricantes Infineon Technologies AG　
Logotipo Infineon Technologies AG Logotipo



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User’s Manual, DS1.1, Oct. 2003
FALC®56
E1/T1/J1 Framer and Line Interface
Component for Long- and Short-Haul
Applications
PEF 2256 H/E, Version 2.1
Hardware Description
Wired Communications
Never stop thinking.

1 page




PEF2256 pdf
FALC®56
PEF 2256 H/E
Table of Contents
Page
4.4.7.1
4.4.7.2
4.4.7.3
4.4.7.4
4.4.7.5
4.5
4.5.1
4.5.1.1
4.5.2
4.5.2.1
4.5.3
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
HDLC or LAPD access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Support of Signaling System #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Sa-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Channel Associated Signaling CAS (E1, serial mode) . . . . . . . . . . 104
Channel Associated Signaling CAS (E1, µP access mode) . . . . . . 104
System Interface in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Receive System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Receive Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Transmit System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Transmit Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Time Slot Assigner (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Test Functions (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Pseudo-Random Binary Sequence Generation and Monitor . . . . . . . . 117
Remote Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Payload Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Single Channel Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Alarm Simulation (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Single Bit Defect Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5 Functional Description T1/J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1 Receive Path in T1/J1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.1
Receive Line Interface (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.2
Receive Short and Long-Haul Interface (T1/J1) . . . . . . . . . . . . . . . . . 122
5.1.3
Receive Equalization Network (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1.4
Receive Line Attenuation Indication (T1/J1) . . . . . . . . . . . . . . . . . . . . 123
5.1.5
Receive Clock and Data Recovery (T1/J1) . . . . . . . . . . . . . . . . . . . . . 123
5.1.6
Receive Line Coding (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1.7
Receive Line Termination (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.8
Receive Line Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.1.9
Loss-of-Signal Detection (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.1.10
Receive Jitter Attenuator (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.1.11
Jitter Tolerance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.12
Output Jitter (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1.13
Framer/Synchronizer (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1.14
Receive Elastic Buffer (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1.15
Receive Signaling Controller (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.15.1
HDLC or LAPD Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.15.2
Support of Signaling System #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.15.3
CAS Bit-Robbing (T1/J1, serial mode) . . . . . . . . . . . . . . . . . . . . . . . 141
5.1.15.4
CAS Bit-Robbing (T1/J1, µP access mode) . . . . . . . . . . . . . . . . . . . 141
5.1.15.5
Bit Oriented Messages in ESF-DL Channel (T1/J1) . . . . . . . . . . . . 141
5.1.15.6
4 kbit/s Data Link Access in F72 Format (T1/J1) . . . . . . . . . . . . . . . 142
User’s Manual
Hardware Description
5
DS1.1, 2003-10-23

5 Page





PEF2256 arduino
FALC®56
PEF 2256 H/E
List of Figures
Page
Figure 43
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Figure 81
Figure 82
Figure 83
Figure 84
Single Channel Loop-Back (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Receive Clock System (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Receiver Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Receive Line Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Protection Switching Application (T1/J1) . . . . . . . . . . . . . . . . . . . . . . 127
Long Haul Protection Switching Application (T1/J1) . . . . . . . . . . . . . 128
Jitter Attenuation Performance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . 131
Jitter Tolerance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
The Receive Elastic Buffer as Circularly Organized Memory . . . . . . 137
Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . 140
Influences on Synchronization Status (T1/J1) . . . . . . . . . . . . . . . . . . 145
Transmitter Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Clocking in Remote Loop Configuration (T1/J1) . . . . . . . . . . . . . . . . 162
Transmit Clock System (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Transmit Line Monitor Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . 167
System Interface (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Receive System Interface Clocking (T1/J1) . . . . . . . . . . . . . . . . . . . . 174
SYPR Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . . 176
SYPR Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . . 176
RFM Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . . . 177
RFM Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . . . 177
2.048 MHz Receive Signaling Highway (T1/J1). . . . . . . . . . . . . . . . . 178
Receive FS/DL-Bits in Time Slot 0 on RDO (T1/J1) . . . . . . . . . . . . . 178
1.544 MHz Receive Signaling Highway (T1/J1). . . . . . . . . . . . . . . . . 179
Transmit System Clocking: 1.544 MHz (T1/J1) . . . . . . . . . . . . . . . . . 180
Transmit System Clocking: 8.192 MHz/4.096 Mbit/s (T1/J1) . . . . . . . 181
2.048 MHz Transmit Signaling Clocking (T1/J1) . . . . . . . . . . . . . . . . 182
1.544 MHz Transmit Signaling Highway (T1/J1) . . . . . . . . . . . . . . . . 182
Signaling Marker for CAS/CAS-CC Applications (T1/J1) . . . . . . . . . . 183
Signaling Marker for CAS-BR Applications (T1/J1) . . . . . . . . . . . . . . 184
Transmit FS/DL Bits on XDI (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . 185
SYPX Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . . 186
SYPX Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . . 186
Remote Loop (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Payload Loop (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Local Loop (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Channel Loop-Back (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
HDLC Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
HDLC Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Interrupt Driven Data Transmission (flow diagram) . . . . . . . . . . . . . . 217
Interrupt Driven Transmission Example . . . . . . . . . . . . . . . . . . . . . . . 217
Interrupt Driven Reception Sequence Example . . . . . . . . . . . . . . . . . 218
User’s Manual
Hardware Description
11
DS1.1, 2003-10-23

11 Page







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