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PDF PEEL22CV10A-7 Data sheet ( Hoja de datos )
| Número de pieza | PEEL22CV10A-7 | |
| Descripción | CMOS Programmable Electrically Erasable Logic Device | |
| Fabricantes | ETC | |
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Commercial/
Industrial
PEEL™ 22CV10A-7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
s High Speed/Low Power
- Speeds ranging from 7ns to 25ns
- Power as low as 30mA at 25MHz
s Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
s Development/Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
General Description
The PEEL™22CV10A is a Programmable Electrically Eras-
able Logic (PEEL™) device providing an attractive alterna-
tive to ordinary PLDs. The PEEL™22CV10A offers the
performance, flexibility, ease of design and production
practicality needed by logic designers today. The
PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP
and 28-pin PLCC packages (see Figure 1), with speeds
ranging from 7ns to 25ns and with power consumption as
low as 30mA. EE-reprogrammability provides the conve-
nience of instant reprogramming for development and a
reusable production inventory, minimizing the impact of
programming changes or errors. EE-reprogrammability
s Architectural Flexibility
- 132 product term X 44 input AND array
- Up to 22 inputs and 10 outputs
- Up to 12 configurations per macrocell
- Synchronous preset, asynchronous clear
- Independent output enables
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
s Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Enhanced Architecture fits more logic
than ordinary PLDs
also improves factory testability, thus ensuring the highest
quality possible. The PEEL™22CV10A is JEDEC file com-
patible with standard 22V10 PLDs. Eight additional configu-
rations per macrocell (a total of 12) are also available by
using the “+” software/programming option (i.e.,
22CV10A+). The additional macrocell configurations allow
more logic to be put into every design. Programming and
development support for the PEEL™22CV10A are pro-
vided by popular third-party programmers and develop-
ment software. ICT also offers free PLACE development
software.
Figure 1. Pin Configuration
DIP
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I
Figure 2. Block Diagram
PLCC
*Optional extra ground pin for
-7/I-7 speed grade.
SOIC
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04-02-009F
1 page  
PEELTM 22CV10A
Figure 5. Four Configurations of the PEEL™22CV10A I/O Macrocell
Table 1. PEEL™ 22CV10A Macrocell Configuration Bits
Configuration
# AB
1 00
2 10
3 01
4 11
Input/Feedback Select
Register Feedback
Bi-Directional I/O
Output Select
Register
Combinatorial
Active Low
Active High
Active Low
Active High
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04-02-009F
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PEEL22CV10A-7.PDF ] | |
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