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PDF PEB2447 Data sheet ( Hoja de datos )

Número de pieza PEB2447
Descripción Memory Time Switch Extended Large MTSXL
Fabricantes Siemens Semiconductor Group 
Logotipo Siemens Semiconductor Group Logotipo



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No Preview Available ! PEB2447 Hoja de datos, Descripción, Manual

ICs for Communications
Memory Time Switch Extended Large
MTSXL
PEB 2447 Version 1.2
Data Sheet 03.97
T2447-XV12-D2-7600

1 page




PEB2447 pdf
1.2 Logic Symbol
PEB 2447
Overview
Figure 1
Functional Symbol
1.3 General Device Overview
The Siemens Memory Time Switch Extended Large MTSXL (PEB 2447) is a capacity
expansion of the MTSL (PEB 2047). It is a monolithic CMOS switching device capable
of connecting maximally 2048 PCM input time slots to 2048 output time slots. In order to
manage the problem of different line delays, six additional FS inputs can be used as
frame measurement inputs and 16 different input offsets of PCM frames are allowed.
Thus a frame wander can be compensated by adjusting the input offset during operation.
A special circuitry guarantees that no bit error will occur, when reprogramming the input
offsets.
The MTSXL on chip connection memory and data memory are accessed via the 8-bit
standard µP interface (Intel demultiplexed type).
A built-in selftest mechanism – also activated by the µP – ensures proper device
operation in the system.
The PEB 2447 is fabricated using the advanced CMOS technology from Siemens and is
mounted in a P-MQFP-100-2 package. Inputs and outputs are TTL compatible.
Semiconductor Group
5
03.97

5 Page





PEB2447 arduino
PEB 2447
Functional Description
2 Functional Description
The MTSXL is a memory time switch device. Operating with a device clock of
16.384 MHz it can connect any of 2048 PCM input channels to any of 2048 output
channels.
A general block diagram of the MTSXL is shown in figure 3.
2.1 General Operation
The input information of a complete frame is stored twice in the two on-chip 16-kbit data
memories DM 0 and DM 1 (Data Memory 0 and Data Memory 1). The incoming
2048 channels of 8 bits each are written in sequence into fixed positions of DM 0 and
DM 1. This is controlled by the input counter in the timing control block with a 8 kHz
repetition rate.
For outputting, two connection memories (CM 0 and CM 1) are read in sequence
synchronously. Each entry in the connection memory CM 0 / CM 1 points to a location
in data memory DM 0 / DM 1. The byte in this data memory location is transferred into
the current output time slot. The read access to the CM’s is controlled by an output
counter. CM 0 supplies the PCM data for outputs OUT0 to OUT15, CM 1 supplies the
PCM data for outputs OUT16 to OUT31.
Semiconductor Group
11
03.97

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