|
|
Número de pieza | PEB22320N | |
Descripción | Primary Rate Access Clock Generator and Transceiver PRACT | |
Fabricantes | Siemens Semiconductor Group | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PEB22320N (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! ICs for Communications
Primary Rate Access Clock Generator and Transceiver
PRACT
PEB 22320
Version 2.1
Data Sheet 04.95
1 page Primary Rate Access Clock Generator
and Transceiver
PRACT
Preliminary Data
PEB 22320
CMOS
1 Features
• ISDN line interface for 1544 and 2048 kbit/s (T1 and
CEPT)
• Data and clock recovery
• Transparent to ternary codes
• Low transmitter output impedance for a high return
loss with reasonable protection resistors (CCITT
G.703 requirements for the line input return loss
fulfilled)
P-LCC-44
• Adaptively controlled receiver threshold
• Programmable pulse shape for T1 applications
• Jitter specifications of CCITT I.431 and BELLCORE
TR-NWT-000499 publications met
• Wander and jitter attenuation
• Jitter tolerance of receiver: 0.5 UI s
• Implements local and remote loops for diagnostic purposes
• Monolithic line driver for a minimum of external components
• Low power, reliable CMOS technology
• Loss of signal indication for receiver
• Clock generator for system clocks
Type
PEB 22320 N
Ordering Code
Q67100-A6059
Package
P-LCC-44 (SMD)
The Primary Rate Access Clock Generator and Transceiver PRACT (PEB 22320) is a
monolithic CMOS device which implements the analog receive and transmit line
interface functions to primary rate PCM carriers. It may be programmed or hard wired to
operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems.
The PRACT recovers clock and data using an adaptively controlled receiver threshold.
It will meet the requirement of CCITT I.431 and Bellcore TR-NWT-000499 Issue 5,
December 1993 (Transport System Generic Requirements) in case of pulse shape, jitter
tolerance and jitter transfer characteristic.
Semiconductor Group
5
04.95
5 Page 2 Functional Description
PEB 22320
Functional Description
RL1
Receive
Input
RL2
XL1
Transmit
Output
XL2
LL XTAL1, 2, 3, 4
Receiver
Clock &
Data
RRCLK
P
Recovery N
Loss of
Signal
Detection
LOS
Jitter Attenuator
&
Clock Generator
Driver
D/A
Timing &
ROM Pulseshaper
LS0, 1, 2
XTIP
Transmit
XTIN
Test Data
XCLK (T1)
System
Clocks
RCLK
RDOP
RDON
XDIP
XDIN
XCLK
(CEPT)
RL ITB04876
Figure 2
Functional Block Diagram of the PRACT
Semiconductor Group
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet PEB22320N.PDF ] |
Número de pieza | Descripción | Fabricantes |
PEB22320 | Primary Rate Access Clock Generator and Transceiver PRACT | Siemens Semiconductor Group |
PEB22320N | Primary Rate Access Clock Generator and Transceiver PRACT | Siemens Semiconductor Group |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |