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PDF PEB22320N Data sheet ( Hoja de datos )

Número de pieza PEB22320N
Descripción Primary Rate Access Clock Generator and Transceiver PRACT
Fabricantes Siemens Semiconductor Group 
Logotipo Siemens Semiconductor Group Logotipo



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No Preview Available ! PEB22320N Hoja de datos, Descripción, Manual

ICs for Communications
Primary Rate Access Clock Generator and Transceiver
PRACT
PEB 22320
Version 2.1
Data Sheet 04.95

1 page




PEB22320N pdf
Primary Rate Access Clock Generator
and Transceiver
PRACT
Preliminary Data
PEB 22320
CMOS
1 Features
• ISDN line interface for 1544 and 2048 kbit/s (T1 and
CEPT)
• Data and clock recovery
• Transparent to ternary codes
• Low transmitter output impedance for a high return
loss with reasonable protection resistors (CCITT
G.703 requirements for the line input return loss
fulfilled)
P-LCC-44
• Adaptively controlled receiver threshold
• Programmable pulse shape for T1 applications
• Jitter specifications of CCITT I.431 and BELLCORE
TR-NWT-000499 publications met
• Wander and jitter attenuation
• Jitter tolerance of receiver: 0.5 UI s
• Implements local and remote loops for diagnostic purposes
• Monolithic line driver for a minimum of external components
• Low power, reliable CMOS technology
• Loss of signal indication for receiver
• Clock generator for system clocks
Type
PEB 22320 N
Ordering Code
Q67100-A6059
Package
P-LCC-44 (SMD)
The Primary Rate Access Clock Generator and Transceiver PRACT (PEB 22320) is a
monolithic CMOS device which implements the analog receive and transmit line
interface functions to primary rate PCM carriers. It may be programmed or hard wired to
operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems.
The PRACT recovers clock and data using an adaptively controlled receiver threshold.
It will meet the requirement of CCITT I.431 and Bellcore TR-NWT-000499 Issue 5,
December 1993 (Transport System Generic Requirements) in case of pulse shape, jitter
tolerance and jitter transfer characteristic.
Semiconductor Group
5
04.95

5 Page





PEB22320N arduino
2 Functional Description
PEB 22320
Functional Description
RL1
Receive
Input
RL2
XL1
Transmit
Output
XL2
LL XTAL1, 2, 3, 4
Receiver
Clock &
Data
RRCLK
P
Recovery N
Loss of
Signal
Detection
LOS
Jitter Attenuator
&
Clock Generator
Driver
D/A
Timing &
ROM Pulseshaper
LS0, 1, 2
XTIP
Transmit
XTIN
Test Data
XCLK (T1)
System
Clocks
RCLK
RDOP
RDON
XDIP
XDIN
XCLK
(CEPT)
RL ITB04876
Figure 2
Functional Block Diagram of the PRACT
Semiconductor Group
11

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