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PDF PEB2096 Data sheet ( Hoja de datos )

Número de pieza PEB2096
Descripción Octal Transceiver for UPN Interfaces OCTAT-P
Fabricantes Siemens Semiconductor Group 
Logotipo Siemens Semiconductor Group Logotipo



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No Preview Available ! PEB2096 Hoja de datos, Descripción, Manual

ICs for Communications
Octal Transceiver for UPN Interfaces
OCTAT-P
PEB 2096 Version 1.3
Data Sheet 01.96
T2096-V13-D2-7600

1 page




PEB2096 pdf
PEB 2096
1 Overview
A Line Card or a PBX consists of a line card controller, multiple layer-1 transceivers for
t/r (a/b), S/T, UP and U2B1Q interfaces, signaling controllers, a microprocessor, memory,
power supply, transformers, etc. The new Siemens generation of highly integrated
ISDN circuits enables design Engineers to decrease board size and thus PBX size and
its production costs.
Figure 1 shows an example of a PBX for up to 16 ISDN and 16 analog subscribers with
4 trunk lines realized with a few highly integrated chips of the new Siemens family of PBX
and Line Cards ICs: ELIC, SICOFI-4, OCTAT-P, QUAT-S and IDEC.
ELIC, Enhanced Line Card Controller, PEB 20550, comprises the following functional
blocks on a single chip:
• Extended PCM Interface Controller (EPIC-1), which can switch up to 32 digital (ISDN)
or 64 voice (analog) subscribers,
• Two HDLC interface controllers (SACCO-A and SACCO-B),
• One D-channel arbiter to multiplex one HDLC controller (SACCO-A) to multiple
subscribers.
The ELIC is a CMOS device offered in a P-MQFP-64 package.
OCTAT-P
The Octal Transceiver for UPN interfaces, PEB 2096, implements the two-wire UPN
interface used to link voice/data digital terminals to PBX subscriber lines. The OCTAT-P
is an optimized device for LT applications and can handle up to eight UPN interfaces
simultaneously. It handles the UPN interfaces in accordance with the UP0 interface
specification except for the reduced loop length.
The OCTAT-P is a CMOS device offered in a P-MQFP-44 package.
QUAT-S
The Quadruple Transceiver for S/T Interfaces, PEB 2084, implements 4 four-wire S/T
interfaces to link voice/data digital terminals to PBX subscriber lines or PBX trunk lines
to the public ISDN. It can handle up to four S/T interfaces simultaneously in accordance
with CCITT I.430, ETSI 300.012, and ANSI T1.605 standards.
The QUAT-S is a CMOS device offered in a P-MQFP-44 package.
IDEC
The ISDN D-Channel Exchange Controller, PEB 2075, is an HDLC controller which
handles four HDLC communication channels. Each channel is fully independent and
programmable by its own register set.
The IDEC is a CMOS device offered in a P-LCC-44 and P-DIP-28 package.
Semiconductor Group
5
01.96

5 Page





PEB2096 arduino
PEB 2096
1.4 Pin Definitions and Functions
Pin No.
Symbol Input (I)
Output (O)
6, 12, 22, 28,
34, 44
3, 9, 19,
25, 31, 37
VDD
VSS
I
I
33, 32
30, 29
27, 26
24, 23
1, 2
4, 5
7, 8
10, 11
LI0a,b
LI1a,b
LI2a,b
LI3a,b
LI4a,b
LI5a,b
LI6a,b
LI7a,b
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
43 FSC I
42 DCL I
41 DD I
40 DU O
39 IDS I
16 TMS I
15 TCK I
14 TDI I
13 TDO O
20 XTAL1 I
21 XTAL2 O
36 CLK1 O
35 CLK2 O
38 RST I
Function
+ 5 V power supply
Reference ground
UPN Line Interfaces a,b
No. 0: differential input / output
No. 1: differential input / output
No. 2: differential input / output
No. 3: differential input / output
No. 4: differential input / output
No. 5: differential input / output
No. 6: differential input / output
No. 7: differential input / output
IOM®-2 Interface
Frame Synchronization Clock: 8 kHz
Data Clock
Data Downstream (data input)
Data Upstream (data output)
Interface Data rate Select (static pin-strapped):
0: double DCL (normal IOM interface)
1: single DCL
JTAG Boundary Scan Interface
Test Mode Select, internal pull-up resistor
Test Clock
Test Data Input, internal pull-up resistor
Test Data Output
Oscillator or 15.36 MHz clock input
Oscillator output
Clock output 15.36 MHz
(i.e. to drive other OCTAT-P)
Clock output 7.68 MHz
(i.e. to drive ISAC-S or QUAT-S)
Reset, active high
Semiconductor Group
11
01.96

11 Page







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