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PDF LCK4801 Data sheet ( Hoja de datos )
| Número de pieza | LCK4801 | |
| Descripción | Low-Voltage HSTL Differential Clock | |
| Fabricantes | Agere Systems | |
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Preliminary Data Sheet
July 2001
LCK4801
Low-Voltage HSTL Differential Clock
General
The LCK4801 is a low-voltage, 3.3 V HSTL
differential clock synthesizer. The LCK4801 supports
two differential HSTL output pairs with frequencies
from 336 MHz to 1 GHz. The clock is designed to
support single and multiple processor systems that
require HSTL differential inputs. The LCK4801
contains a fully integrated PLL (phase-locked loop)
which multiplies the HSTL_CLK or PECL_CLK input
frequency to match individual processor clock
frequencies. The PLL can be bypassed so that the
PCLK outputs are fed from the HSTL_CLK or
PECL_CLK input for test purposes. All outputs are
powered from a 2 V external supply to reduce on-
chip power consumption. All outputs are HSTL. The
PLL can operate in the internal feedback mode, or in
the external feedback mode for board level
debugging applications.
Features
s Two fully selectable clock inputs.
s Fully integrated PLL.
s 336 MHz to 1 GHz output frequencies.
s HSTL outputs.
s HSTL and LVPECL reference clocks.
s 32-pin TQFP package.
Description
PCLK0_EN (PULL-UP)
PCLK1_EN (PULL-UP)
TESTM (PULL-UP)
PLLREF_EN (PULL-UP)
REF_SEL (PULL-UP)
HSTL_CLK (PULL-UP)
HSTL_CLK (PULL-UP)
PECL_CLK (PULL-UP)
PECL_CLK (PULL-UP)
(PULL-UP)
EXTFB_IN (HSTL)
(PULL-DOWN)
EXTFB_EN (PULL-UP)
SEL[4:0] (PULL-UP)
RESET (PULL-UP)
PLL_BYPASS (PULL-UP)
1
0
0
/M
1
PLL
0
1
/N
DECODE
0
1
Figure 1. LCK4801 Logic Diagram
PCLK0
PCLK0 (HSTL)
PCLK1
PCLK1 (HSTL)
EXTFB_OUT
EXTFB_OUT (HSTL)
2274.a (F)
1 page  
Preliminary Data Sheet
July 2001
LCK4801
Low-Voltage HSTL Differential Clock
Pin Information (continued)
Table 3. Function Control
Control Pin
REF_SEL
TESTM
PLLREF_EN
PLL_BYPASS
EXTFB_EN
PCLK0_EN
PCLK1_EN
RESET
SEL[4:0]
0
HSTL_CLK.
M divider test mode enabled.
Disable the input to the PLL and reset
the M divider.
Outputs fed by input reference or M
divider.
External feedback enabled.
PCLK0 = low, PCLK0 = high.
PCLK1 = low, PCLK1 = high.
Resets feedback N divider.
See Table 2 on page 4.
1
PECL_CLK.
Reference fed to bypass MUX.
Enable the input to the PLL.
Outputs fed by VCO.
Internal feedback enabled.
PCLK0 = high, PCLK0 = low.
PCLK1 = high, PCLK1 = low.
Feedback enabled.
See Table 2 on page 4.
Absolute Maximum Characteristics
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Table 4. Absolute Maximum Ratings
Parameter
Power Supply
Input Voltage
Write Current
Storage Temperature
Symbol
VDDD/VDDA
VDDHSTL
VIN
IIN
TS
Min
–0.5
–0.5
–0.5
–1
–50
Typical
—
—
—
—
—
Max
4.4
4.4
VDDD + 0.3
1
150
Unit
V
V
mA
°C
Agere Systems Inc.
5
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