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PDF LC89978M Data sheet ( Hoja de datos )
| Número de pieza | LC89978M | |
| Descripción | CCD Delay Line for Multi-System | |
| Fabricantes | Sanyo | |
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Ordering number : EN5546A
CMOS LSI
LC89978M
CCD Delay Line for Multi-System
Overview
The LC89978M is a CCD delay line for multi television
system that incorporates a comb filter to remove noise
from the chrominance signal and a 1-H delay line for the
luminance signal.
Features
• 5-V single-voltage power supply
• Built-in 4 × PLL frequency multiplier circuit allows 4fsc
operation from an fsc (3.58 MHz) input.
• Can be switched between the NTSC/M, PAL/GBI, and
PAL/M formats by setting control pin values.
• Includes a built-in crosstalk exclusion comb filter for the
chrominance signal that provides high-precision comb
characteristics in an adjustment-free circuit.
• Peripheral circuits provided on chip for operation with a
minimum of external components.
• Positive-phase signal input, positive-phase signal output
(luminance signal)
Package Dimensions
unit: mm
3111-MFP14S
[LC89978M]
Functions
• CCD shift registers (for chrominance and luminance
signals)
• Timing generator and clock driver for CCD
• Delay time selective circuit
• CCD signal adder
• Auto-bias circuit
• Sync tip clamp circuit (luminance signal)
• Center bias circuit (chrominance signal)
• Sample-and-hold circuit
• 4 × PLL frequency multiplier circuit
• 4fsc clock output circuit
• High voltage generator for CCD Reset Drain (RD).
SANYO: MFP14S
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD
Pd max
Topr
Tstg
Conditions
Ratings
–0.3 to +6.0
250
–10 to +60
–55 to +125
Unit
V
mW
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
73097HA (OT)/N3096HA (OT) No. 5546-1/7
1 page  
LC89978M
Test Conditions
1. The supply current with no input signal
2. The pin output voltage (the center bias voltage) with no input signal
3. Measure the C-OUT output when a 350-mVp-p sine wave is input to C-IN1 and C-IN2.
C-OUT output [mVp-p]
GVC = 20log
——————————
350 [mVp-p]
[dB]
Test frequencies:
GVC-1: 4.431395 MHz (PAL/GBI)
GVC-2: 3.571628 MHz (PAL/M)
GVC-3: 3.571628 MHz (NTSC/M)
4. Measure the comb depth from the C-OUT output when a 350-mVp-p sine wave with frequency fa is input to C-IN1
and C-IN2, and when a sine wave of frequency fb is input.
The C-OUT output for an fb input [mVp-p]
CD
=
20log
——————————————————
The C-OUT output for an fa input [mVp-p]
[dB]
Test Frequencies
fa fb
CD-1: 4.431395 MHz (PAL/GBI)
GD-2: 3.571628 MHz (PAL/M)
GD-3: 3.571628 MHz (NTSC/M)
4.435303 (PAL/GBI)
3.575561 (PAL/M)
3.563761 (NTSC/M)
5. Measure the C-OUT output when a 200-mVp-p sine wave is input to C-IN1 and C-IN2, and when a 500-mVp-p sine
wave is input, and calculate the gain difference as follows:
( The output for a 500-mVp-p input [mVp-p]
LNC = 20log
——————————————————
500 [mVp-p]
Test Frequencies
LNC-1
LNC-2
LNC-3
4.431395MHz (PAL/GBI)
3.571628MHz (PAL/M)
3.571628MHz (NTSC/M)
)The output for a 200-mVp-p input [mVp-p]
—————————————————— [dB]
200 [mVp-p]
6. Measure the 4fsc (14.3 MHz) and fsc (3.58 MHz) components in the C-OUT output with no input signal.
7. Measure the noise in the C-OUT output with no input signal.
Measure the noise with a noise meter with a 200-kHz high-pass filter and a 5-MHz low-pass filter.
8. Input a 350-mVp-p sine wave to C-IN1 and C-IN2. Let V1 be the C-OUT output when SW3 is set to the ‘a’ position,
and let V2 be the C-OUT output when SW3 is set to the 'b' position.
V2 [mVp-p] – V1 [mVp-p]
ZOC =
——————————— × 500 [dB]
V1 [mVp-p]
Test Frequencies
ZOC-1: 4.431395 MHz (PAL/GBI)
ZOC-2: 3.571628 MHz (PAL/M)
ZOC-3: 3.571628 MHz (NTSC/M)
9. The delay time in the C-OUT output with respect to the C-IN1 input. This is the CCD 1.5-bit delay.
10. The pin output voltage (clamp voltage) with no input signal.
No. 5546-5/7
5 Page | ||
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