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PDF LC89977M Data sheet ( Hoja de datos )
| Número de pieza | LC89977M | |
| Descripción | CCD Delay Line for PAL | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : EN5545
MOS LSI
LC89977M
CCD Delay Line for PAL
Preliminary
Overview
The LC89977M is CCD delay line for PAL television
system that includes a chrominance signal crosstalk
exclusion filter and a luminance signal 1-H delay line on
chip.
Features
• 5-V single-voltage power supply
• Built-in 3 × PLL frequency multiplier circuit allows 3fsc
operation from an fsc (4.43 MHz) input.
• Can be switched between the PAL/GBI, and 4.43NTSC
formats by setting control pin values.
• Includes a built-in crosstalk exclusion comb filter for the
chrominance signal that provides high-precision comb
characteristics in an adjustment-free circuit.
• Peripheral circuits provided on chip for operation with a
minimum of external components.
• Positive-phase signal input, positive-phase signal output
(luminance signal)
Package Dimensions
unit: mm
3111-MFP14S
[LC89977M]
Functions
• CCD shift registers (for chrominance and luminance
signals)
• Timig generator and clock driver for CCD
• Delay time selective circuit
• CCD signal adder
• Auto-bias circuit
• Sync tip clamp circuit (luminance signal)
• Center bias circuit (chrominance signal)
• Sample-and-hold circuit
• 3 × PLL frequency multiplier circuit
• 3fsc clock output circuit
• High voltage generator for CCD Reset Drain (RD)
SANYO: MFP14S
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD
Pd max
Topr
Tstg
Conditions
Ratings
–0.3 to +6.0
250
–10 to +60
–55 to +125
Unit
V
mW
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
N3096HA(OT) No. 5545-1/7
1 page  
LC89977M
5. Measure the C-OUT output when a 200-mVp-p sine wave is input to C-IN1 and C-IN2, and when a 500-mVp-p sine
wave is input, and calculate the gain difference as follows:
( The output for a 500-mVp-p input [mVp-p]
LNC = 20log
——————————————————
500 [mVp-p]
Test Frequencies
LNC-1 4.429662MHz (PAL/GBI)
LNC-2 4.425694MHz (4.43NTSC)
)The output for a 200-mVp-p input [mVp-p]
—————————————————— [dB]
200 [mVp-p]
6. Measure the 3fsc (13.3 MHz) and fsc (4.43 MHz) components in the C-OUT output with no input signal.
7. Measure the noise in the C-OUT output with no input signal.
Measure the noise with a noise meter with a 200-kHz high-pass filter and a 5-MHz low-pass filter.
8. Input a 350-mVp-p sine wave to C-IN1 and C-IN2. Let V1 be the C-OUT output when SW3 is set to the ‘a’ position,
and let V2 be the C-OUT output when SW3 is set to the 'b' position.
V2 [mVp-p] – V1 [mVp-p]
ZOC =
——————————— × 500 [dB]
V1 [mVp-p]
Test Frequencies
ZOC-1: 4.429662 MHz (PAL/GBI)
ZOC-2: 4.425694 MHz (4.43NTSC)
9. The delay time in the C-OUT output with respect to the C-IN1 input. This is the CCD 1-bit delay.
10. The pin output voltage (clamp voltage) with no input signal.
11. Measure the Y-OUT output with a 200-kHz 400-mVp-p sine wave input to Y-IN.
Y-OUT output [mVp-p]
GVY = 20log
—————————— [dB]
400 [mVp-p]
12. Measure the Y-OUT output when a 200-kHz 200-mVp-p sine wave is input to Y-IN, and when a 3.3-MHz
200-mVp-p sine wave is input.
The Y-OUT output for a 3.3-MHz input [mVp-p]
GFY = 20log
—————————————————————
The Y-OUT output for a 200-kHz input [mVp-p]
[dB]
Here, adjust Vbias so that the clamp level is +250 mV.
13. Apply a 5-step staircase wave (as in the figure below) to Y-IN, and measure the differential gain and differential
phase in the Y-OUT output using a vector scope.
No. 5545-5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LC89977M.PDF ] | |
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