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PDF LC895994 Data sheet ( Hoja de datos )
| Número de pieza | LC895994 | |
| Descripción | CD-R Encoder/Decoder LSI with Built-in ATAPI (IDE) Interface | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : EN*5824
Preliminary
CMOS IC
LC895994
CD-R Encoder/Decoder LSI with
Built-in ATAPI (IDE) Interface
Overview
The LC895994 is a CD-R LSI that provides a wide range
of functions including CD-ROM decoding (including
ECC) and encoding, subcode Q encoding (CRC addition)
and decoding, CD encoding, ATIP decoding and CLV
servo, and an IDE interface that includes the register
block.
Features
• ECC and EDC correction/addition for the CD-ROM
data (during decoding and encoding)
• ATIP decoding and CRC checking for both encoding
and decoding
• CLV servo control using ATIP data during encoding
• CIRC code insertion and EFM modulation during
encoding
• Support for PCA random EFM output during encoding
• Support for CD-ReWritable (CD-RW) Write Strategy
signal output
• Access to buffer RAM from microcontroller via
LC895994
• Built-in ATAPI (IDE) interface
• Speeds of 12× for decoding and 4× for encoding
— Frequencies
Decoding: 17.2872 MHz
Encoding: 17.2872 MHz without Write Strategy
support
69.1488 MHz with Write Strategy
support
• IDE Transfer rate: 13.3 MB/s when using 16-bit data
path 80-ns DRAM chips
• Buffer RAM sizes between 1 and 32 megabits (using 16-
bit DRAMs)
• User control over sizes of CD main channel, C2 flag
areas in buffer RAM
• Built-in batch transfer function for transferring entire
CD main channel, C2 flag, or subcode area in a single
operation
• Built-in multiblock transfer function for transferring
multiple blocks in a single operation
Package Dimensions
unit: mm
3153A-QFP160E
[LC895994]
SANYO: QIP160E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
42098RM (OT) No. 5824-1/7
1 page  
LC895994
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin
Pin No.
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Pin Name
IO9
IO10
IO11
IO12
IO13
IO14
IO15
VSS
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
VDD
VSS
RAS0
RAS1
CAS0
CAS1
OE
UWE
LWE
TEST0
VDD
EXCK
WFCK
SBSO
SCOR
VSS
BCK
SDATA
LRCK
C2PO
VDD
VSS
HRST
DASP
CS3FX
CS1FX
VDD
DA2
DA0
PDIAG
Type
Description
B
B
B
B Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors
B
B
B
P
O
O
O
O
O
Address signal pins for ROM encoder/decoder DRAM
O
O
O
O
O
P
P
O
DRAM RAS signal output pins
O
O
DRAM CAS signal output pins
O
O DRAM output enable signal output pin
O DRAM upper write enable signal output pin
O DRAM lower write enable signal output pin
I Test pin (connect to VSS)
P
O Subcode data read shift clock output pin
I Subcode frame synchronization input pin
I Subcode serial data input pin
I Subcode block synchronization input pin
P
I Serial data input clock input pin
I Serial data input pin
I 44.1-kHz strobe signal input pin
I C2 pointer input pin
P
P
I
B
IDE pins
I
I
P
I
I IDE pins
B
Continued on next page.
No. 5824-5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LC895994.PDF ] | |
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