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PDF LC895925 Data sheet ( Hoja de datos )
| Número de pieza | LC895925 | |
| Descripción | Signal Processing LSI for CD-R Drives | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : EN*5784
CMOS LSI
LC895925
Signal Processing LSI for CD-R Drives
Preliminaly
Overview
The LC895925 provides the following signal processing
functions for CD-R drives: CD-ROM decoding/encoding
(complete with ECC processing for the former), subcode
decoding/encoding, CD encoding, ATIP decoding, CLV
servo, and SCSI interface registers.
Features
• CD-ROM decoding/encoding complete with error
detection and error correction
• Subcode decoding/encoding complete with error
correction
• ATIP decoding and CRC checking for both encoding
and decoding
• CLV servo control using ATIP data during encoding
• CIRC code insertion and EFM modulation during
encoding
• Support for PCA random EFM output during encoding
• Support for CD-ReWritable (CD-RW) Write Strategy
signal output
• Access to buffer RAM from microcontroller via
LC895925
• Built-in SCSI interface
• Speeds of 12× for decoding and 4× for encoding
— Frequencies
Decoding: 17.2872 MHz
Encoding: 17.2872 MHz without Write Strategy
support
69.1488 MHz with Write Strategy
support
• Transfers speeds of 10 megabytes/s (synchronous) and 5
megabytes/s (asynchronous) with 16 80-ns DRAMs *1
• Buffer RAM sizes between 1 and 32 megabits (using 16-
bit DRAMs)
• User control over sizes of CD main channel, C2 flag,
and subcode areas in buffer RAM
• Built-in batch transfer function for transferring entire
CD main channel, C2 flag, or subcode area in a single
operation
• Built-in multiblock transfer function for transferring
multiple blocks in a single operation
Notes:
1. Using a SCSI master clock of 20 MHz with speeds up
to 8×.
2. Using a SCSI master clock of 17.2872 MHz with
speeds up to 4×.
Package Dimensions
unit: mm
3153A-QFP160E
[LC895925]
SANYO: QIP160E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
D1997RM (OT) No. 5784-1/7
1 page  
LC895925
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin
Pin Number
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Pin Name
IO9
IO10
IO11
IO12
IO13
IO14
IO15
VSS
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
VDD
VSS
RAS0
RAS1
CAS0
CAS1
OE
UWE
LWE
TEST0
VDD
EXCK
WFCK
SBSO
SCOR
VSS
BCK
SDATA
LRCK
C2PO
VDD
VSS
DB0
DB1
VDD
DB2
DB3
VSS
DB4
DB5
Type
Description
B
B
B
B Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors
B
B
B
P
O
O
O
O
O
Address signal pins for ROM encoder/decoder DRAM
O
O
O
O
O
P
P
O
DRAM RAS signal output pins
O
O
DRAM CAS signal output pins
O
O DRAM Output Enable signal output pin
O DRAM Output Upper Write Enable signal output pin
O DRAM Output Lower Write Enable signal output pin
I Test pin (connect to VSS)
P
O Subcode data read shift clock output pin
I Subcode frame synchronization input pin
I Subcode serial data input pin
I Subcode block synchronization input pin
P
I Serial data input clock input pin
I Serial data input pin
I 44.1-kHz strobe signal input pin
I C2 pointer input pin
P
P
B
SCSI pins
B
P
B
SCSI pins
B
P
B
SCSI pins
B
Continued on next page.
No. 5784-5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LC895925.PDF ] | |
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