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PDF LC895196K Data sheet ( Hoja de datos )

Número de pieza LC895196K
Descripción ATA-PI Compatible CD-ROM Decoder IC
Fabricantes Sanyo 
Logotipo Sanyo Logotipo



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No Preview Available ! LC895196K Hoja de datos, Descripción, Manual

Ordering number : EN *5852
CMOS LSI
LC895196K
ATA-PI Compatible CD-ROM Decoder IC
Preliminary
Overview
The LC895196K is a large scale integrated circuit
equipped with CD-ROM functions and an internal ATA-
PI (IDE) interface.
Functions
• CD-ROM ECC functions, SUB-CODE read function,
ATA-PI (IDE) interface (Registers, etc.).
Features
• Built-in ATA-PI (IDE) interface.
• 32× speed supported
Uses the EDO-DRAM (× 16, 50 ns)
16.6 Mbyte/s (with IORDY)
Operating frequency: 33.8688 MHz
• 24× speed supported
Uses the EDO-DRAM (× 16, 60 ns)
16.6 Mbyte/s (without IORDY)
Operating frequency: 33.8688 MHz
• Supports between 1 Mbit and 4 Mbit of buffer RAM
when DRAM is used
• The user can flexibly set the CD main channel, the C2
flags, and the subcode regions in the buffer RAM
• Built-in batch transfer function. (Where the batch
transfer function is a function that transmit the CD main
channel, C2 flags, subcodes, etc. all at once.)
• Built-in multitransmit function. (Where the
multitransmit function is a function that automatically
transmits multiple blocks at once.)
• Built-in intelligent functions (auto buffering, auto
decoding, CD-R compatibility)
• Built in subcode P-W buffering function (NO-ECC) and
CD-TEXT compatibility
Package Dimensions
unit: mm
3214-SQFP144
[LC895196K]
SANYO: SQFP144
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter
Maximum power supply voltage
I/O voltage
Allowable power dissipation
Operating temperatures
Storage temperatures
Soldering temperature (terminals only)
I/O current
Note: * Per basic I/O cell
Symbol
VDD max
VI, VO
Pd max
Topr
Tstg
II, IO max
Ta = 25°C
Ta = 25°C
Ta 70°C
For 10 seconds
Condition
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
550
–30 to +70
–55 to +125
235
±20*
Unit
V
V
mW
°C
°C
°C
mA
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3097HA (OT) No. 5852-/12

1 page




LC895196K pdf
LC895196K
Continued from preceding page.
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
C2PO
SDATA
BCK
LRCK
EXCK
WFCK
SBSO
VDD
VSS0
SCOR
MCK
TEST0
TEST1
CSEL
ZRSTIC
CSCTRL
MCK2
MCK3
VSS0
XTALCK0
XTAL0
VSS0
VDD
ZRESET
ZRD
ZWR
ZCS
VSS0
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
D0
D1
D2
D3
VDD
VSS0
D4
D5
D6
D7
ZINT0
ZINT1
ZSWAIT
ZRSTCPU
XTAL1
Type
Function
I
I
CD-DSP interface
I
I
O
I Subcode I/O
I
P
P
I Subcode I/O
NC
NC
NC
O XTALCK1 1/1, 1/2 and STOP output
I
I Test input pin. Connect to VSS.
I ATAPI control signal
O Reset signal to the drive reset IC
I Microcontroller-side CS active low/high select pin
O XTALCK0 1/1, 1/2, 1/5, 1/512 and STOP output
O XTALCK0 1/1, 1/5, 2/5, 1/512 and STOP output
P
NC
I X’tal oscillator circuit input
O X’tal oscillator circuit input
P
P
I LSI reset
I Microcontroller data read signal input
I Microcontroller data write signal input
I Input pin for the register chip select signal from the microcontroller
P
I
I
I
I Microcontroller register select signals
I
I
I
B
B Microcontroller data signals.
B Built-in pull-up resistors.
B
P
P
B
B Microcontroller data signals.
B Built-in pull-up resistors.
B
O Output pin for interrupt request signal to the microcontroller (set by the ECC-side registers)
O Output pin for interrupt request signal to the microcontroller (set by the ATAPI-side registers)
O Wait signal to the microcontroller
O Reset signal to the CPU
I X’tal oscillator circuit input
Continued on next page.
No. 5852-5/12

5 Page





LC895196K arduino
LC895196K
D7 to D0 (input/output)
This is the MC-side data bus. Built-in pull-up resistor.
ZINT (output)
This is the interrupt signal to the microcontroller.
3. The Buffer RAM
IO0 to IO15 (input/output)
This is the buffer DRAM data bus. Built-in pull-up resistors.
RA0 to RA8 (output)
These are the address pins for the buffer RAM.
ZRAS0 (output)
These are the RAS output pins for the buffer DRAM.
ZCAS0 and ZCAS1 (output)
This is the CAS output pin for the buffer DRAM. Normally ZCAS0 is used. When two 1M (64K × 16 bit) DRAMS
are used, connect the ZCAS0 output to the CAS pin of each DRAM. When the 2CAS types is used, connect ZCAS0
to UCAS and connect ZCAS1 to LCAS.
ZOE (output)
The read output signal for the buffer DRAM.
ZUWE, ZLWE (output)
This is the write output signal for the buffer DRAM. This connects to various DRAM pins. When the 2CAS type is
used, connect ZLWE to the write enable signal.
4. Subcode Interface
EXCK, WFCK, SBSO, SCOR (input or output)
These are the subcode interface pins. By connecting these to the CD-DSP the subcode data is accepted by the
LC895196K and transferred to the host.
5. The CD-DSP Data
BCK, SDATA, LRCK, C2PO (input)
When connected to CD-DSP, CD-ROM data is acquired. C2PO is a pin for use by the C2 flag.
6. Other Pins
ZRESET (input)
This is the LC895196K reset pin. The LC895196K is reset when this signal is low. This signal must be kept low for
at least a period of 1 µs after power on.
XTALCK0, XTAL0
These cause oscillation at 33.8688 MHz. Frequencies from the outside may also be input into XTALCK0.
XTALCK1, XTAL1
Basically, these pins cannot oscillate. If these pins are not used, connect XTALCK1 (pin 100) to ground.
MCK (output)
This outputs the XTALCK1 and XTALCK1/2 frequencies. The output can also be turned off.
No. 5852-11/12

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