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PDF LC895194 Data sheet ( Hoja de datos )

Número de pieza LC895194
Descripción CD-ROM Error Correction LSI with On-Chip ATA-PI (IDE) Interface
Fabricantes Sanyo 
Logotipo Sanyo Logotipo



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No Preview Available ! LC895194 Hoja de datos, Descripción, Manual

Ordering number : EN*5154B
Preliminary
CMOS LSI
LC895194
CD-ROM Error Correction LSI
with On-Chip ATA-PI (IDE) Interface
Functions
CD-ROM error detection and correction, ATA-PI (IDE)
interface (including the register and other blocks)
Features
• ATA-PI (IDE) interface
• Supports 16×-speed playback (with IORDY): Using 16×
70 ns DRAMs
• 16.6 MB/s transfer rate: Using 16× 70 ns DRAMs
• Supports the use of from 1 M to 32 M of buffer RAM.
(DRAM)
• Allows the user to arbitrarily set the CD main channel
and C2 flag areas in buffer RAM.
• Batch transfer function (function for transferring the CD
main channel and C2 flag data in one operation)
• Multi-transfer function (function for sending multiple
blocks in one operation)
Package Dimensions
unit: mm
3214-SQFP144
[LC895194]
SANYO: SQFP144
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter
Maximum supply voltage
I/O voltages
Allowable power dissipation
Operating temperature
Storage temperature
Soldering heat resistances (pins only)
I/O power
Note: * Per cell for basic I/O cells
Symbol
VDD max
VI, VO
Pd max
Topr
Tstg
II, IO
Ta = 25°C
Ta = 25°C
Ta 70°C
10 seconds
Conditions
Allowable Operating Ranges at Ta = –30 to +75°C, VSS = 0 V
Parameter
Supply voltage
Input voltage range
Symbol
VDD
VIN
Conditions
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
550
–30 to +75
–55 to +125
235
±20*
Unit
V
V
mW
°C
°C
°C
mA
min typ max Unit
4.5 5.0
5.5 V
0
VDD
V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
N3097HA(OT) /81095HA (OT) No. 5154-1/7

1 page




LC895194 pdf
LC895194
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Pin No.
Symbol
Type
Function
52
VSS0
P
53
VSS0
P
54
TEST4
I Test input. This pin must be tied low.
55
VSS0
P
56
VSS0
P
57
ZINT1
O Interrupt request signal output to the microcontroller from the IDE block
58
VSS0
P
59
VSS0
P
60
VSS0
P
61 NC
62 NC
63
VSS0
P
64
SDATA
I
65
BCK
I
CD-DSP interface
66
LRCK
I
67
C2PO
I
68
MCK2
O XTALCK 1/1, 1/2, 1/512, and stop output
69
VSS0
P
70
XTALCK
I Crystal oscillator input
71
XTAL
O Crystal oscillator output
72
VSS0
P
73
VDD
P
74
MCK
O XTALCK 1/1, 1/2, and stop output
75
VSS0
P
76
ZRSTIC
O Reset signal to drive reset IC
77
CSCTRL
I Selects active high or active low for the microcontroller CS line.
78
ZRESET
I LSI reset
79
ZRD
I Microcontroller data read signal input
80
ZWR
I Microcontroller data write signal input
81
ZCS
I Input for the register chip select signal from the microcontroller
82
VSS0
P
83
SUA0
I
84
SUA1
I
85
SUA2
I
86
SUA3
I Microcontroller register select signals
87
SUA4
I
88
SUA5
I
89
SUA6
I
90
VDD
P
91
VSS0
P
92 D0 B
93 D1 B
94 D2 B
95 D3 B Microcontroller data signals
96 D4 B These pins have built-in pull-up resistors.
97 D5 B
98 D6 B
99 D7 B
100 ZINT O Interrupt request signal output to the microcontroller
Note: 1. NC (no connection) pins must be left open.
2. Pin names (signal names) that begin with a Z have negative (inverted) logic.
3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground.
Continued on next page.
No. 5154-5/7

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