PDF LC89515K Data sheet ( Hoja de datos )

Número de pieza	LC89515K
Descripción	CD-ROM/CD-I Error Correction/ Host Interface LSI
Fabricantes	Sanyo
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No Preview Available ! Ordering number : EN4272C CMOS LSI LC89515K CD-ROM/CD-I Error Correction/ Host Interface LSI Overview The LC89515K is a version of the LC8951 in which certain aspects of the internal registers have been improved to make them even easier to use in CD-ROM and CD-I products. The basic blocks are identical to those in the LC8951 and these products are software and pin compatible. Thus this product can replace the LC8951 without change. (However, this product is provided in a slightly different package: a short lead type QIP-80E as opposed to the QIP-80A.) The LC89515K is an error correction and host interface LSI for use in CD-ROM and CD-I products. This product integrate in a single chip all CD-ROM specific functions, including the error correction that was previously implemented in software on a microprocessor and the CD player and host computer interfaces that were previously implemented in discrete components or gate arrays. The use of the LSI can provide significant improvements in CD-ROM and CD-I players, including increased transfer rates, miniaturization, increased reliability, an improved cost performance ratio, and a more efficient development period. Features • Software and pin compatibility with the LC8951 (Changes were made to internal registers, the SRAM interface, and other aspects.) • Support for CD-ROM (mode 1) and CD-I (mode 2, forms 1 and 2) • All CD-ROM/CD-I special functions implemented on a single chip • Hardware error detection and correction for high speed, without relying on software • Real-time error correction: Error correction and detection are possible without interrupting the host interface bus. • Fast transfers: up to 2.3 MB/s (18.4 Mb/s) • Support for low-speed hosts (multiple block buffering) • Built-in host interface command FIFO (for easy SCSI support) • Built-in 12-byte status FIFO • CMOS circuits, single 5 V power supply Package Dimensions unit: mm 3174-QFP80E [LC89515K] SANYO: QIP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O2095HA (OT)/12395TH (OT)/ 61394TH No. 4272-1/6 1 page LC89515K Write RS AR No. Symbol BIT7 0 —— AR 0000 R0 SBOUT msb 0001 R1 IFCTRL CMDIEN 0010 R2 0011 R3 DBCL DBCH B7 0100 0101 0110 R4 R5 R6 DACL DACH DTTRG A7 A15 0111 R7 1 1000 R8 1001 R9 1010 R10 DTACK WAL WAH CTRL0 A7 A15 DECEN 1011 R11 CTRL1 SYIEN 1100 R12 1101 R13 1110 R14 PTL PTH CTRL2 A7 A15 0 1111 R15 RESET Note: The values of the shaded bits are ignored. BIT6 — DTEIEN B6 A6 A14 A6 A14 SYDEN A6 A14 0 BIT5 — DECIEN B5 A5 A13 BIT4 — CMDBK B4 A4 A12 BIT3 A3 — DTWAI B3 B11 A3 A11 BIT2 A2 — STWAI B2 B10 A2 A10 BIT1 A1 — DOUTEN B1 B9 A1 A9 BIT0 A0 lsb SOUTEN B0 B8 A0 A8 A5 A13 E01RQ DSCREN A5 A13 0 A4 A12 AUTORQ COWREN A4 A12 BCKSL A3 A11 ERAMRQ MODRQ A3 A11 DLAEN A2 A10 WRRQ FORMRQ A2 A10 0 A1 A9 QRQ MBCKRQ A1 A9 STENCTL A0 A8 PRQ SHDREN A0 A8 STENTRG 6. Additional Registers Write [R14] CTRL2: Control 2 STENCTL (STEN control) 0.........The external STEN pin goes to 0 when the microprocessor writes one byte of status information. (This is identical to LC8951 operation.) 1.........The external STEN pin goes to 0 due to 0 being written to the STENTRG register when the microprocessor writes * bytes of status information. This bit is set to 0 on reset. STENTRG (STEN trigger) This bit is only valid when STENCTL is 1. The external STEN pin goes to 0 when a 0 is written to this bit. This bit is reset when the host reads the last byte, i.e., when the external STEN pin has become 1. DLAEN (drive last address enable) When WRRQ is set to 0 during buffering, buffering continues until the next SYNC signal arrives and then stops. This results in the sectors that are buffered when WRRQ was set to 0 becoming valid. (This bit is set to 0 on reset.) BCKSL (bit clock select) Setting this bit to 1 allows the bit clock from the CD-DSP to be inverted. (SDATA is acquired on the rising edge of BCK.) (This bit is set to 0 on reset.) No. 4272-5/6 5 Page

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