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PDF LC895124 Data sheet ( Hoja de datos )
| Número de pieza | LC895124 | |
| Descripción | CD-ROM Driver with On-Chip SCSI Interface and Subcode Functions | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : EN*5240
Preliminary
CMOS LSI
LC895124
CD-ROM Driver with On-Chip SCSI Interface and
Subcode Functions
Overview
The LC895124 is the next-generation version of the
LC89512 and is a CD-ROM decoder that includes a SCSI
interface that supports the high-speed transfers (10 MB/s)
of the FAST SCSI standard.
Functions
CD-ROM ECC function, subcode read function, SCSI
interface
Features
• On-chip SCSI interface (with built-in SCAM selection
register)
• Supports 8× playback - Using ×16 80-ns DRAMs
• Supports 4× playback - Using ×16 80-ns DRAMs or ×8
70-ns DRAMs
• Transfer rates: 10 MB/s (synchronous), 5 MB/s
(asynchronous) using ×16 80-ns DRAMs*1
• Transfer rates: 8.467 MB/s (synchronous), 4.2336 MB/s
(asynchronous) using ×8 70-ns DRAMs*2
• PSRAM can be used, providing 5 MB/s transfers in
synchronous mode and 5 MB/s transfers in
asynchronous mode .
• Supports the connection of up to 32 Mb of buffer RAM
(using DRAM) (Up to 2 Mb when PSRAM is used)
• The user can freely set the CD main channel, C2 flag,
and other areas in buffer RAM.
• Batch transfer function (transfers the CD main channel
and C2 flag data in a single operation)
• Multi-block transfer function (automatically transfers
multiple blocks in a single operation)
• High-speed transfer mode supports a 10-MB/s
(synchronous) transfer rate using ×8 80-ns DRAMs
• Subcode ECC function
Note: 1. For speeds up to 8× speed, use a SCSI master
clock frequency of 20 MHz.
Note: 2. For speeds up to 4× speed, use a SCSI master
clock frequency of 16.9344 MHz.
Package Dimensions
unit: mm
3214-SQFP144
[LC895124]
SANYO: SQFP144
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter
Maximum supply voltage
I/O voltages
Allowable power dissipation
Operating temperature
Storage temperature
Soldering heat resistances (pins only)
Symbol
VDD max
VI, VO
Pd max
Topr
Tstg
Ta = 25°C
Ta = 25°C
Ta ≤ 70°C
10 seconds
Conditions
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
450
–30 to +70
–55 to +125
260
Unit
V
V
mW
°C
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
22896HA (OT) No. 5240-1/8
1 page  
LC895124
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
TEST3
TEST4
ZRESET
VDD
VSS0
CSCTRL
X1EN
XTALCK1
XTAL1
ZSWAIT
VDD
VSS0
D0
D1
D2
D3
D4
D5
D6
D7
ZRD
VSS0
VDD
ZWR
ZCS
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
ZINT0
ZINT1
VDD
VSS1
DB0
VSS1
DB1
DB2
VSS1
DB3
Type
I
I
I
P
P
I
I
I
O
O
P
P
B
B
B
B
B
B
B
B
I
P
P
I
I
I
I
I
I
I
I
I
O
O
NC
NC
NC
NC
NC
P
P
NC
NC
NC
B
P
B
B
P
B
Function
Test pins. These pins must be connected to VSS0.
LSI reset. The LSI is reset on a 0 input.
Selects active-high or active-low for the microcontroller CS logic.
Selection pin that must be set to 1 when XTALCK1 is used.
SCSI block oscillator circuit input. Selected by X1EN.
SCSI block oscillator circuit output.
WAIT signal output to the microcontroller
Microcontroller data signals
Microcontroller data read signal input
Microcontroller data write signal input
Input for the register chip select signal from the microcontroller
Register chip select signal from the microcontoller
Interrupt request output to the microcontroller (ECC side. Set with a register.)
Interrupt request output to the microcontroller (SCSI side. Set with a register.)
SCSI connection
SCSI connection
SCSI connection
Note: 1. NC pins must be left open. Do not connect any signal to these pins.
2. Pin names that start with Z are negative-logic signals.
3. VSS0 is the logic system ground and VSS1 is the SCSI interface ground.
4. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any
other measures necessary to prevent undershoot in the DRAM related circuits.
5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied.
Continued on next page.
No. 5240-5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LC895124.PDF ] | |
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