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PDF LC876572 Data sheet ( Hoja de datos )

Número de pieza LC876572
Descripción 8-Bit Single Chip Microcontroller with 72/64 KB ROM and 2048-Byte RAM On Chip
Fabricantes Sanyo 
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No Preview Available ! LC876572 Hoja de datos, Descripción, Manual

Ordering number : ENN*6716
CMOS IC
LC876572A/64A
8-Bit Single Chip Microcontroller with
72/64 KB ROM and 2048-Byte RAM On Chip
Preliminary
Overview
The LC876572A and LC876564A are 8 bit single chip microcontrollers with the following on-chip functional blocks :
- CPU: operable at a minimum bus cycle time of 100 ns
- On-chip ROM Maximum Capacity : LC876572A 72K bytes
LC876564A 64K bytes
- On-chip RAM: 2048 bytes
- VFD automatic display controller / driver
- 16 bit timer / counter (can be divided into two 8 bit timers)
- 16 bit timer / PWM (can be divided into two 8 bit timers)
- timer for use as date / time clock
- synchronous serial I/O port (with automatic block transmit / receive function)
- asynchronous / synchronous serial I/O port
- 12-channel × 8-bit AD converter
- Weak signal detector
- 15-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read-Only Memory (ROM): LC876572A
LC876564A
73728 × 8 bits
65536 × 8 bits
(2) Random Access Memory (RAM): LC876572A/64A 2048 × 9 bits
(3) Minimum Bus Cycle Time: 100 ns (10 MHz)
Note: The bus cycle time indicates ROM read time.
Ver.1.05
12000
91400 RM (IM) SK No.6716-1/23

1 page




LC876572 pdf
Pin Assignment
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LC876572A/64A
50 S19/PC3
49 S18/PC2
48 S17/PC1
47 S16/PC0
46 VDD3
45 S15/T15
44 S14/T14
43 S13/T13
42 S12/T12
41 S11/T11
40 S10/T10
39 S9/T9
38 S8/T8
37 S7/T7
36 S6/T6
35 S5/T5
34 S4/T4
33 S3/T3
32 S2/T2
31 S1/T1
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E Ver.1.00
SANYO : QIP-100E
No.6716-5/23

5 Page





LC876572 arduino
LC876572A/64A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol
Pins
Conditions
Operating
VDD(1)
supply voltage
range
Hold voltage VHD
Pull-down
voltage
Input high
voltage
VP
VIH(1)
VIH(2)
VIH(3)
VIH(4)
VIH(5)
VIH(6)
VIH(7)
VDD1=VDD2=VDD3
=VDD4
0.294µs tCYC
200µs
VDD1
VP
RAM and the
register data are
kept in HOLD
mode.
•Port 0,3: CMOS output Output disable
option
•Port 8
Port 0,3: N-ch open drain Output disable
output
•Port 1
Output disable
•Port71,72,73
•P70 port input/interrupt
S16 to S51
Output P-channel
Tr. OFF
P70 Weak signal input Output disable
Port 70
Output disable
Watchdog timer
XT1, XT2, CF1, RES
Ratings
VDD[V] min. typ. max.
4.5 6.0
2.0 6.0
4.5–6.0 -35
4.5–6.0 0.3VDD
+0.7
4.5–6.0
4.5–6.0
0.3VDD
+0.7
0.3VDD
+0.7
4.5–6.0 0.3VDD
+1.0
4.5–6.0 0.75VDD
4.5–6.0 0.9VDD
4.5–6.0 0.75VDD
VDD
VDD
13.5
VDD
VDD
VDD
VDD
VDD
unit
V
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
VIL(7)
Operation
cycle time
tCYC
External system fEXCF(1)
clock
frequency
•Port 0,3: CMOS output Output disable
option
•Port 8
Port 0,3: N-ch open drain Output disable
output
•Port 1
Output disable
•Port 71,72,73
•P70 port input/interrupt
S16 to S51
Output P-channel
Tr. OFF
Port 87 weak signal input Output disabled
Port 70
Output disabled
Watchdog timer
XT1,XT2,CF1, RES
CF1 •CF2 open circuit
•system clock
divider set to 1/1
•external clock
DUTY = 50±50%
•CF2 open circuit
vsystem clock
divider set to 1/2
Continued/
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
4.5–6.0
VSS
VSS
VSS
-35
VSS
VSS
VSS
0.294
0.1
0.2
0.15VDD
+0.4
0.15VDD
+0.4
0.1VDD
+0.4
0.2VDD
0.25VDD
0.8VDD
-1.0
0.25VDD
200
µs
10 MHz
20
No.6716-11/23

11 Page







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