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PDF LC875024A Data sheet ( Hoja de datos )

Número de pieza LC875024A
Descripción 8-Bit Single Chip Microcontroller with 32/24/16K-Byte EPROM and 640-Byte RAM On Chip
Fabricantes Sanyo 
Logotipo Sanyo Logotipo



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No Preview Available ! LC875024A Hoja de datos, Descripción, Manual

Ordering number : ENN*6713
CMOS IC
LC875032A/24A/16A
8-Bit Single Chip Microcontroller with
32/24/16K-Byte EPROM and 640-Byte RAM On Chip
Preliminary
Overview
The LC875032A/24A/16A microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks:
- CPU: Operable at a minimum bus cycle time of 100ns
- 32K/24K/16K bytes ROM
- 640 byte RAM
- two high performance 16 bit timer/counters (can be divided into 8 bit units)
- two 8 bit timers with prescalers
- timer for use as date/time clock
- one synchronous serial I/O ports (with automatic block transmit/receive function)
- one asynchronous/synchronous serial I/O port
- 12-bit PWM × 2
- 3-channel × 8-bit AD converter
- high speed 8-bit parallel interface
- 16-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM)
- 32512 × 8 bits (LC875032A)
- 24576 × 8 bits (LC875024A)
- 16256 × bits (LC875016A)
Ver.1.03
90198
91400 RM (IM) HK / SY No.6713-1/25

1 page




LC875024A pdf
Pin Assignment
LC875032A/24A/16A
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP
P71/INT1/T0HCP
P72/INT2/T0IN
P73/INT3/T0IN
RES#
XT1
XT2
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LC875032A/24A/16A
QIP
32 PB2/D2
31 PB3/D3
30 PB4/D4
29 PB5/D5
28 PB6/D6
27 PB7/D7
26 P27/INT5/T1IN
25 P26/INT5/T1IN
24 P25/INT5/T1IN
23 P24/INT5/T1IN
22 P23/INT4/T1IN
21 P22/INT4/T1IN
20 P21/INT4/T1IN
19 P20/INT4/T1IN
18 P07
17 P06
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Package Dimension
(unit : mm)
3159
SANYO : QIP-64E
No.6713-5/25

5 Page





LC875024A arduino
LC875032A/24A/16A
Port Output Configuration
Output configuration and pull-up resistor options are shown in the following table.
Input is possible even when port is set to output mode.
Terminal
Option
applies to:
Option
Output Format
Pull-up resistor
P00-P07
1 bit units
1 CMOS
Programmable (Note 1)
2 Nch-open drain
None
P10-P17
each bit
1 CMOS
Programmable
P20-P27
2 Nch-open drain
Programmable
PA2-PA5
each bit
1 CMOS
Programmable
PB0-PB7(*)
PC0-PC7
2 Nch-open drain
Programmable
P70
-
None
Nch-open drain
Programmable
P71-P73
-
None
CMOS
Programmable
P80-P82
-
None
Nch-open drain
None
PWM0,
-
None
CMOS
None
PWM1
XT1
-
None
Input only
None
XT2
-
None Output for 32.768kHz crystal oscillation
None
Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07).
(*) When in parallel interface mode, PB0-PB7 output format is CMOS, regardless of any selected option.
Note: Connect as follows to reduce noise on VDD and increase the back-up time.
VSS1, VSS2 and VSS3 must be connected together and grounded.
Example 1 : In hold mode, during backup, port output ‘H’ level is supplied from the back-up capacitor.
Power
Supply
LSI
VDD1
Back-up capacitor
VDD2
VDD3
VSS1 VSS2 VSS3
Example 2 : During backup in hold mode output is not held high and its value in unsettled.
Power
Supply
Back-up capacitor
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.6713-11/25

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