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PDF LC866548 Data sheet ( Hoja de datos )

Número de pieza LC866548
Descripción 8-Bit Single Chip Microcontroller with One-Time Programmable PROM
Fabricantes Sanyo 
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No Preview Available ! LC866548 Hoja de datos, Descripción, Manual

Ordering number : ENN*6700
CMOS IC
LC866548/40/32/28/24A
8-Bit Single Chip Microcontroller
Preliminary
Overview
- CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond)
- On-chip ROM maximum capacity : 48K bytes
- On-chip RAM capacity : 1152 bytes (LC866548A/40A/32A)
: 896 bytes (LC866528A/24A)
- VFD automatic display controller/driver
- 16-bit timer/counter (or two 8-bit timers)
- 16-bit timer/ PWM (or two 8-bit timers)
- 8-channels × 8 bit AD Converter
- Two 8-bit synchronous serial-interface circuits (1-channel × 16 bit, 1-channel × 8 bit)
- 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM)
: LC866548A
: LC866540A
: LC866532A
: LC866528A
: LC866524A
49152 × 8 bits
40960 × 8 bits
32768 × 8 bits
28672 × 8 bits
24576 × 8 bits
Ver.1.05
71896
91400 RM (IM) SK No.6700-1/21

1 page




LC866548 pdf
Pin Assignment QIP100E
LC866548/40/32/28/24A
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50 S19/PC3
49 S18/PC2
48 S17/PC1
47 S16/PC0
46 VDD3
45 S15/T15
44 S14/T14
43 S13/T13
42 S12/T12
41 S11/T11
40 S10/T10
39 S9/T9
38 S8/T8
37 S7/T7
36 S6/T6
35 S5/T5
34 S4/T4
33 S3/T3
32 S2/T2
31 S1/T1
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
No.6700-5/21

5 Page





LC866548 arduino
LC866548/40/32/28/24A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol
Operating
supply voltage
range
Hold voltage
VDD(1)
VHD
Pull-down
voltage
Input high
voltage
VP
VIH(1)
VIH(2)
VIH(3)
VIH(4)
VIH(5)
Input low
voltage
VIH(6)
VIH(7)
VIH(8)
VIL(1)
VIL(2)
VIL(3)
VIL(4)
Operation
cycle time
VIL(5)
VIL(6)
VIL(7)
tCYC
Pins Conditions
VDD1=VDD2 0.98µs tCYC
=VDD3=VDD4 tCYC 400µs
VDD[V]
Ratings
min. typ. max.
4.5 6.0
unit
V
VDD1=VDD2
VP
RAMs and the
Registers hold voltage
at HOLD mode.
4.5 - 6.0
2.0
-35
6.0
VDD
Port 0 at CMOS
output option
Port 0 at N-ch
open drain output
•Port 1
•Ports 72, 73
•Port 3 at CMOS
output option
Port 3 at N-ch
open drain output
•Port 70
port input
/interrupt
•Port 71
RES
Port 70
Watchdog timer
•Port 8
•Ports 74 , 75
S16 - S51
Port 0 at CMOS
output option
Port 0 at N-ch
open drain output
•Ports 1, 3
•Ports 72, 73
•Port 70
port input
/interrupt
•Port 71
RES
Port 70
Watchdog timer
•Port 8
•Ports 74 , 75
S16 - S51
Output disable
Output disable
Output disable
Output disable Tr.
OFF
Output disable
Output disable
Output disable
Output P-channel Tr.
OFF
Output disable
Output disable
Output disable
Output disable
Output disable
Output disable
Output P-channel Tr.
OFF
4.5 - 6.0 0.33VDD
+1.0
4.5 - 6.0 0.75VDD
4.5 - 6.0 0.75VDD
4.5 - 6.0 0.75VDD
4.5 - 6.0 0.75VDD
4.5 - 6.0 0.9VDD
4.5 - 6.0 0.75VDD
4.5 - 6.0 0.33VDD
+1.0
4.5 - 6.0 VSS
4.5 - 6.0 VSS
4.5 - 6.0 VSS
4.5 - 6.0 VSS
4.5 - 6.0 VSS
4.5 - 6.0 VSS
4.5 - 6.0 VP
4.5 - 6.0 0.98
VDD
13.5
VDD
13.5
VDD
VDD
VDD
VDD
0.2VDD
0.25VDD
0.25VDD
0.25VDD
0.8VDD
-1.0
0.25VDD
0.2VDD
400 µs
(continue)
No.6700-11/21

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