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PDF LC65P29 Data sheet ( Hoja de datos )
| Número de pieza | LC65P29 | |
| Descripción | One-Time Programmable 4-Bit Single-Chip Microcontroller | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : EN5894
CMOS IC
LC65P29
One-Time Programmable 4-Bit Single-Chip
Microcontroller
Overview
The LC65P29 is a one-time programmable (on-chip
PROM) version of Sanyo's LC6529N/F/L 4-bit single-chip
CMOS microcontroller. It provides identical functionality
to, and pin compatibility with, the mask ROM versions of
the LC6529N/F/L, and provides a 1-KB internal PROM.
The LC65P29 is provided in DIP24S and MFP30S plastic
packages and the program can be written by the customer,
thus makes this IC appropriate for the limited-run products
and the startup of initial production of new products.
Furthermore, it can provide reduced changeover periods
when end product specifications change.
Additionally, the LC65P29 can function as a one-time
programmable PROM version of the Sanyo LC6527N/F/L
and LC6528N/F/L by using the 29T27 adapter socket.
Features
• Mask option settings can be switched by setting PROM
data.
All options, except for the port output circuit type can be
set with PROM data.
• 1-KB PROM
• PROM data security function
• Pin compatible with the mask ROM version
• Instruction cycle time: 0.92 µs to 20 µs
• Packages: DIP24S and MFP30S
Package Dimensions
unit: mm
3067-DIP24S(300mil)
[LC65P29]
SANYO: DIP24S(300mil)
unit: mm
3216-MFP30S(375mil)
[LC65P29]
SANYO: MFP30S(375mil)
Note: The package dimension figures are provide for reference purposes
without dimensional tolerances. Contact your Sanyo representative
for the official package dimension figures.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
61298RM (OT) No. 5894-1/14
1 page  
LC65P29
Pin Descriptions
Pin name
VDD
VSS
Number
of pins I/O
Function
Power supply. Must be connected to +5 V
1 — during normal operation.
1 — Power supply. Must be connected to 0 V
during normal operation.
Option
OSC1/CE
OSC2/TA
1.Two-pin RC oscillator
(Single-pin external
I System clock oscillator connections. Leave clock input)
1 OSC2 open and input the external clock to 2.Two-pin ceramic
O OSC1 if an external clock is used.
oscillator
3.Divisor option: 1/1, 1/3,
or 1/4
State during reset
—
—
Function in
PROM mode
EPROM contorol
signal inputs
CE
TA
PA0/A6
PA1/A7
PA2/A8
PA3/A9
4
PC0/D0
PC1/D1
PC2/D2
PC3/D3
PD0/D4
PD1/D5
PD2/D6
PD3/D7
4
4
PE0/CMP0/A0
PE1/CMP1/A1
PE2/CMP2/A2
PE3/CMP3/A3
4
4
VREF0/A4
VREF1/A5/
DASEC
2
RES/VPP/OE
1
TEST/EPMOD 1
• I/O ports A0 to A3
Input in 4-bit units (IP instruction)
Output in 4-bit units (OP instruction)
Data testing in 1-bit units (BP and BNP
instructions)
I/O Data set and clear operations in 1-bit units Open-drain output
(SPB and RPB instructions)
• PA3 is used for standby mode control.
• Applications must assure that chattering
(key bounce) noise is not input during a
HALT instruction execution cycle.
• High-level output (The
n-channel output
transistor turned off.)
• Address inputs
A6 to A9
• I/O ports C0 to C3
1. Open-drain output
I/O
The pin functions are identical to those of
pins A0 to A3.
However, there is no standby mode
control function.
• The output during a reset can be specified
2. High-level output
during reset
3. Low-level output
during reset
• Selection of items 2 or
• High-level output
• Low-level output
(Depending on an
option selection.)
to be either high or low as an option.
3 is in 4-bit units.
• Data I/O
D0 to D3
I/O
• I/O ports D0 to D3
The pin functions are identical to those of
pins PC0 to PC3.
The same as for pins
PC0 to PC3
The same as pins PC0 to • Data I/O
PC3
D4 to D7
• When comparator input is selected:
CMP0 and CMP1 use VREF0 as the
reference voltage,
CMP2 and CMP3 use VREF1 as the
I reference voltage,
• Comparator inputs CMP0 to CMP3
Data input in 4-bit units (IP instruction)
• Data testing in 1-bit units (BP and BNP
instructions)
• When input is selected for port E
• Input ports E0 to E3
I Input in 4-bit units (IP instruction)
• Data testing in 1-bit units (BP and BNP
instructions)
1. Comparator input
2. Port E input
3. No feedback resistor
4. Feedback resistor
present
• Selection of items 1 or
2 is in 4-bit units.
• Items 3 and 4 are only
specified when item 1
is selected.
• Comparator reference voltage inputs
VREF0 and VREF1
VREF0 is the reference voltage input for
CMP0 and CMP1.
I VREF1 is the reference voltage input for
CMP2 and CMP3.
• When PE0/CMP0 to PE3/CMP3 are
selected to function as port E inputs,
these pins are connected to VSS.
• System reset input
• Connect an external capacitor to effect the
I power-on reset.
• Input a low level for at least 4 clock cycles
to effect a reset restart.
• IC test pin
I This pin must be connected to VSS during
normal operation.
• Address inputs
A0 to A3
• Address inputs
A4 and A5
• EPROM control
signal input
DASEC
• EPROM control
signal input
VPP/ OE
• EPROM control
signal input
EPMOD
No. 5894-5/14
5 Page 
LC65P29
Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter
High-level input current
Low-level input current
Low-level output voltage
Symbol
Applicable
pins/notes
IIH1 PA, PC, PD
IIH2 PE
IIH3 OSC1
IIL1 PA, PC, PD
IIL2 PE
IIL3 RES
IIL4 OSC1
VOL1 PA, PC, PD
VOL2 PA, PC, PD
Conditions
VDD [V]
Output n-channel transistor off
(Includes the n-channel
transistor off leakage current)
VIN = 13.5 V
When the port E input option
is selected VIN = VDD
When the RC oscillator and
external clock option is selected
VIN = VDD
Output n-channel transistor off
(Includes the n-channel
transistor off leakage current)
VIN = VSS
When the port E input option
is selected VIN = VSS
VIN = VSS
When the RC oscillator and
external clock option is selected
VIN = VSS
IOL = 10 mA
IOL = 1.8 mA
(When all port I/O levels are
Under 1 mA)
Ratings
min typ
–1.0
–1.0
–80
–1.0
–50
Hysteresis voltage
VHIS1
VIHS2
RES
OSC1*1
When the RC oscillator and
external clock option is selected
0.1 VDD
0.1 VDD
RC oscillator
IDDOP1
IDDOP2
VDD
VDD
IDDOP3 VDD
Figure 2. 850 kHz (TYP)
Figure 2. 400 kHz (TYP)
Figure 3. 4 MHz, 1/1, 1/3, and
1/4 divisor ratios
5
4.5
5
Ceramic oscillator*2
IDDOP4 VDD
IDDOP5 VDD
Figure 3. 2 MHz, 1/1, 1/3, and
1/4 divisor ratios
Figure 3. 800 kHz, 1/1 divisor
ratio
4.5
5
IDDOP6 VDD
Figure 3. 400 kHz, 1/1 divisor
ratio
4.5
External clock*2
IDDOP7 VDD
200 to 4330 kHz, 1/1, 1/3, and
1/4 divisor ratios
5
Standby mode
Oscillator frequency
IDDst1
IDDst2
fMOSC
VDD
VDD
OSC1, OSC2
OSC1, OSC2
Output n-channel transistor off
Port = VDD
Output n-channel transistor off
Port = VDD
Figure 2. Cext = 220 pF ±5%
Rext = 15.0 kΩ ±1%
Figure 2. Cext = 220 pF ±5%
Rext = 6.8 kΩ ±1%
6
3
4 to 6
0.05
0.025
275 400
579 850
OSC1, OSC2 Figure 3. fo = 4 MHz
3840
4000
Oscillator frequency
OSC1, OSC2 Figure 3. fo = 2 MHz
fFOSC*3
OSC1, OSC2 Figure 3. fo = 800 kHz
1920
768
2000
800
OSC1, OSC2 Figure 3. fo = 400 kHz
384 400
Figure 4. fo = 4 MHz
Oscillator stabilization time
tCFS
Figure 4. fo = 2 MHz
fo = 800 kHz
fo = 400 kHz
Pull-up resistor reset port
External reset characteristics:
reset time
Ru
tRST
VIN = VSS
5 70 100
See Figure 6.
Pin capacitance
f = 1 MHz
Cp VIN = VSS for all input pins
other than the measured pin
10
Notes: 1. The OSC1 pin has Schmitt characteristics when the RC oscillator and external clock input oscillator option is selected.
2. The current drain during normal operation with the output n-channel transistors off and the port at VDD.
3. fCFOSC indicates frequencies at which oscillator operation is possible.
Unit
max
5.0 µA
5.0 µA
1.0 µA
µA
µA
µA
µA
1.5 V
0.4 V
V
V
8 mA
7 mA
8 mA
7 mA
8 mA
7 mA
8 mA
10 µA
5 µA
711 kHz
1179
4160
2080
832
416
10
kHz
kHz
kHz
kHz
kHz
ms
10 ms
150 kΩ
ms
pF
No. 5894-11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LC65P29.PDF ] | |
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