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PDF LC6568H Data sheet ( Hoja de datos )
| Número de pieza | LC6568H | |
| Descripción | 8K-Byte ROM-Contained Single-Chip 4-Bit Microcomputers | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LC6568H (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Ordering number: EN2412A
J
iSAiYO
F No. 2412A
LC6568D,
CMOS LSI
6568H
8K-Byte ROM-Contained Single-Chip 4-Bit Microcomputers
with FLT/LED Drivers, Comparator Input
The L C 6 5 6 8 D / H are single-chip 4-bit microcomputers that contain an 8K-byte ROM, 1 K-bit RAM, and have 64 pins.
The LC6568D/H have 57 pins for ports — 28 pins for 7 input/output common ports, 21 pins for 6 output ports, and
8 pins for 2 input ports. The L C 6 5 6 8 D / H have specific ports that are used to provide the interrupt function, 4-bit/8-bit
serial input/output function and burst pulse output function. Each of the 28 pins for input/output common ports
contains a driver with a withstand voltage of 15V max. and a drive current of 15mA max. and each of the 21 pins for
output ports contains a high-voltage output driver of the P-channel open drain type. Since the high-voltage output
driver can be used as general-purpose high-current driver as w e l l as fluorescent tube driver, the L C 6 5 6 8 D / H can be also
w i d e l y used in applications where no fluorescent display is provided.
T h e L C 6 5 6 8 D / H are t h e same as o u r L C 6 5 0 0 series in t h e basic architecture of the CPU and the i n s t r u c t i o n set, b u t are
made more powerful in the stack level and also made easier-to-use in the standby function.
Features
• Instruction set w i t h 81 instructions (Common to the LC6500 series)
• On-chip 8192-byte ROM, 1024-bit RAM
• I n s t r u c t i o n cycle t i m e : 2 . 7 7 /xs (D version, V q d = 4 t o 6 V )
0 . 9 2 Ms (H version, V d d = 4.5 t o 6 V )
• Serial input/output interface x 1 (4 bits/8 bits program-selectable)
I/O ports: 57 pins in all
Input ports
8 pins
Input/output common ports 28 pins: 15V max., 15mA max., LED drivable, pull-up resistance option available
Output ports
21 pins: V Q D - 4 5 V withstand voltage, FLT drivable, common with general-purpose
output, pull-down resistance option available
Output level during reset: For ports C, D, output (H or L) during reset may be specified portwise by option.
Interrupt function
Timer interrupt: 1 line
INTO to 3 pin or serial I/O interrupt: 1 line
Stack level: 8 levels (Common with interrupt)
Timer: 4-bit prescaler +8-bit programmable timer
Burst pulse (64 x cycle time, dury 50%) output function
Oscillator option
Circuit mode: Ceramic resonator mode, RC mode, external clock mode (384kHz to 4.33MHz)
Predivider option: 1/1, 1/3,1/4
Standby function: Standby function provided by the H A L T instruction. Provides the function to absorb the OSC
stabilizing time in the ceramic resonator mode.
Supply Voltage: 4 to 6V (D version)
4.5 to 6V (H version)
Package:
DIP 64 shrink type,QIP64A
Evaluation LSI: LC6595 (Evaluation chip) + EVA800-TB6568 (Evaluation chip board),
LC65PG68 (Piggyback)
4-channel comparator input
4-channel external interrupt input (1 vector)
SANYO Electric Co.,Ltd. Semiconductor Business Headquarters
TOKYO OFFICE Tokyo Bldg.,1-10,1 Chome, Ueno, Taito-ku,TOKYO, 110 J A P A N
9071JN/3307KI.TS
No.2412-1/31
1 page  
,LC6568D, 6568HI
Pin Description
Pin Name
VDD
vss
0SC1
OSC2
PA0
PAT
PA2
PA3
PBo/INTo
PB1/INT1
PB2/INT2
PB3/INT3
PCo
PC!
PC2
PC3
PD0
PD1
PD2
PD3
PE0
PE1
PE2
PE3
Pins I/O
Functions
Options
During Reset
1 Power supply
1-
-
1 Input • Pin for externally connecting R, (1) External clock input
C or a ceramic resonator for
(2) 2-pin RC OSC
system clock generation.
(3) 2-pin ceramic
1 Output • For the external clock mode, the
resonator OSC
OSC2 pin is open.
(4) Predivider option
1: No predivider
2: 1/3 predivider
3: 1/4 predivider
-
-
4 Input • Input port Ao to 3
(Low-threshold input)
4-bit input (IP instruction)
Single-bit decision (BP, BNP
instructions)
-
-
4 Input • Input port Bo to 3
4-bit input (IP instruction)
Single-bit decision (BP, BNP
instructions)
• Standby is controlled b y the
PB3.
• The PB3 pin must be free from
chattering during the HALT
instruction execution cycle.
• PBoto3: Common with
INToto 3
Program-selectable
(1 interrupt vector, 4 senses)
• Individual inter-
rupt flag (INTOF
to INT3F): Reset
• Individual inter-
- rupt enable flag
(INTOENto
INT3EN):
Disable mode
4 Input/ • Input/output common port
Output
Co to 3.
4-bit input (IP instruction)
4-bit output (OP instruction)
Single-bit decision (BP, BNP
instructions)
Single-bit set/reset (SPB, RPB
instructions)
• Output ( " H " or " L " ) during
reset may be specified by
option.
(1) Open drain type
output
(2) With pull-up
resistance
(3) Output during reset:
"H"
(4) Output during reset:
• " H " output
• " L " output
(Option-select-
able)
• (1), (2):
Specified bit by bit.
• (3), (4):
Specified in a group of
4 bits.
4 I n p u t / • I n p u t / o u t p u t c o m m o n p o r t D o Same as f o r t h e PCo t o 3. Same as f o r t h e PCo
Output
to 3.
to 3.
The functions, options are the
same as f o r t h e PCo t o 3.
4 Input/ • Input/output common port Eo (1) Open drain type
" H " output
Output
to 3.
output
4-bit input (IP instruction)
(2) With pull-up
4-bit output (OP instruction)
resistance
Single-bit decision (BP, BNP
(1), (2): Specified bit by
instructions)
bit.
Single-bit set/reset (SPB, RPB
instructions)
• PEO: With burst pulse (64Tcyc)
output function
Continued on next page
No. 2412-5/31
5 Page 
No. 2412-10/31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LC6568H.PDF ] | |
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