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PDF LC5824 Data sheet ( Hoja de datos )
| Número de pieza | LC5824 | |
| Descripción | 4-Bit Single-Chip Microcontrollers Featuring 4 KB to 8 KB of ROM / 1 Kbit of RAM / and an LCD Driver for Medium Speed Small-Scale Control Applications | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : EN5944
CMOS IC
LC5824, LC5823, LC5822
4-Bit Single-Chip Microcontrollers Featuring 4 KB to 8 KB of ROM, 1 Kbit of RAM,
and an LCD Driver for Medium Speed Small-Scale Control Applications
Overview
The LC5822, LC5823, and LC5824 are CMOS
microcontrollers that feature the low-voltage operation
required for battery-power applications and that provide
4 KB, 6 KB, or 8 KB of ROM, 1 kilobit of RAM, and an
LCD driver.
These microcontrollers support an instruction set based on
that of the earlier LC5800, LC5812, and LC5814 for
excellent efficiency in software development.
Applications
• LCD display in multi-function watches, timers, and
other products
• Control and LCD display in timers
• Control and LCD display in miniature test equipment,
health maintenance equipment, and other products
• These microcontrollers are optimal for products that
include an LCD display, especially battery powered
products.
Features
• These microcontrollers are high-end versions of the
LC5800 and provide the following features.
Low Current Drain * In halt mode (typical)
• Ceramic oscillator 400 kHz (3.0 V) 200 µA
• Crystal oscillator 32 kHz (1.5 V, Ag specifications)
3.0 µA (LCD biases other than 1/3) 4.5 µA (LCD drive:
1/3 bias)
• Crystal oscillator 32 kHz (3.0 V, Li specifications)
2.0 µA (LCD biases other than 1/3) 6.0 µA (LCD drive:
1/3 bias)
Timer and Counter Functions
• One 8-bit programmable timer (May be used as an event
counter)
• One 8-bit programmable reload timer
• Time base timer (for clocks)
• Watchdog timer
• 8-bit serial I/O (3-pin synchronous system)
Wide Allowable Operating Ranges
Power
options
supply
EXT-V
EXT-V
EXT-V
EXT-V
Li
Ag
Cycle
times
Supply
voltage
range
Notes
When an 800-kHz ceramic
10 µs VDD = 2.3 to 3.6 V oscillator is used
When an 400-kHz ceramic
20 µs VDD = 2.3 to 3.6 V oscillator is used
When an 65-kHz crystal oscillator
61 µs VDD = 2.3 to 3.6 V is used
When an 32-kHz crystal oscillator
122 µs VDD = 2.0 to 3.6 V is used
When an 32-kHz crystal oscillator
122 µs VDD = 2.6 to 3.6 V* is used
When an 32-kHz crystal oscillator
122 µs VDD = 1.3 to 1.65 V is used
Note*: When the backup flag is set, the BAK pin is connected to VDD.
Standby Functions
• Clock standby function (halt mode)
Only the oscillator circuits, the divider circuit, and the
LCD driver operate. All other internal operations are
stopped. This provides a power-saving function in which
current drain is minimized, and allows a clock function
to be implemented easily with low power dissipation.
Furthermore, low-speed and high-speed modes can be
implemented by setting the operating modes of the two
oscillator circuits.
• Full standby function (hold mode)
• Halt mode can be cleared by any of two external and
two internal interrupts.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
82198RM (OT) No. 5944-1/24
1 page  
System Block Diagram
LC5824, LC5823, LC5822
Voltage step-
Accumulator
(AC) (4 bits)
Serial I/O
Data I/O - D bus
B register
(4 bits)
Alarm tone
generator
OPG
(2 bits)
Program
counter
(13 bits)
Interrupt control
Table
reference
Timer 1
Timer 2
Carrier control circuit
Watchdog timer
Clock timer
(15 bits)
Reset
circuit
Segment decoder Chronograph
strobe decoder
circuit
LCD driver
Chronograph
control circuit
Switch-
ing
circuit
Crystal
oscillator
circuit
(32 kHz/65 kHz)
CF/RC oscillator
circuit
(400 kHz to
4 MHz)
System clock
generator
RAM: Data memory
ROM: Program memory
DP: Data pointer register
BNK: Bank register
APG: RAM page flag
AC: Accumulator
ALU: Arithmetic and logic unit
B: B register
OPG: ROM page flag
PC: Program counter
IR: Instruction register
STS1: Status register 1
STS2: Status register 2
STS3: Status register 3
STS4: Status register 4
PLA: Programmed logic array used for segment data and strobe functions
WAIT.C: Wait time counter
No. 5944-5/24
5 Page 
Crystal Oscillator Circuit Options
Option
LC5824, LC5823, LC5822
Circuit type
Notes
Used at 32 kHz
The resistor RD is built into the IC when this
circuit is used at 32 kHz.
Used at 38 kHz
Used at 65 kHz
Input Port Options
Option
Circuit type
Low level hold
transistor
selection
Pull-down resistor
Low level
hold transistor
RES Pin
Option
Pull-up resistor,
pull-down
resistor,
resistors left
open, and level
selections
Circuit type
Pull-up resistor
Pull-down resistor
• The cycle time is 4 times n times the f1
period. (n:2)
• The divider circuit outputs (ø1 through ø15)
are used as the clock time base, the LCD
drive frequency generation clock, and for
S/K port chattering prevention.
• OSC1 is stopped by the execution of a
SLOW instruction.
Bus
SF2/RF2, D2 to D7
Output mode
Notes
When use of the hold transistor is selected, it
is used to minimize the current drain that
flows in the pull-down resistor when a push-
button switch is used with S1 or a slide switch
is used with S2.
• When the input open specifications are
selected, before reading the input, the pull-
down transistor is turned on. Then the input
state is read and the pull-down transistor is
turned off. If the input was in the floating
state, the low level hold transistor operates
to hold the level.
If use of the hold transistor is not selected:
• The circuit is used with the pull-down
transistor turned on.
• Select unused if the external control signal
line connected to this input will never be in
the floating state.
Notes
Internal resistor and polarity selections
• Reset on low, pull-up resistor included
• Reset on high, pull-down resistor included
• Reset on low, no resistors connected
• Reset on high, no resistors connected
No. 5944-11/24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LC5824.PDF ] | |
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