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PDF LC4101C Data sheet ( Hoja de datos )
| Número de pieza | LC4101C | |
| Descripción | LCD Dot Matrix Segment Driver for STN Displays | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : EN5280A
CMOS LSI
LC4101C
LCD Dot Matrix Segment Driver
for STN Displays
Overview
The LC4101C is a segment driver for large-scale dot
matrix LCD panels. It latches 240 bits of display data sent
from the controller over a 4-bit or 8-bit parallel connection
and generates the LCD drive signals. The LC4100C and
LC4101C form a large-screen LCD panel driver chip set.
Features
• Fabricated in a CMOS (P-sub) high-voltage process.
• LCD drive voltage: 36 V
• Logic system power-supply voltage: 3.0 to 5.5 V
• fcp max: 12 MHz (VDD = 5 V ±10 %), 6.5 MHz (VDD
= 3 to 4.5 V)
• 240 outputs
• Parallel input switchable between 4 and 8 bits
• DISPOFF function that locks the drive voltages output
to the LCD at fixed levels.
• Display duty: 1/160 to 1/480
Specifications
Absolute Maximum Ratings at Ta = 25°C ± 2°C, standard VSS, VEEn = VEE1 or VEE2, VSSn = VSS1 or VSS2
Parameter
Supply voltage
Input voltage
Operating temperature
Storage temperature
Symbol
VDD
VEEn
VSSn
VIN
V0, V2
V3
V5
Topr
Tstg
Conditions
D0 to D7, LOAD, CP, L/R, BS, TEST,
DISP, DF, EIO1, EIO2
V0, V2
V3
V5
Ratings
–0.3 to +7
–0.3 to +40
–0.3 to +0.3
–0.3 to VDD + 0.3
VEEn – 7 to VEEn + 0.3
–0.3 to VSSn + 7
–0.3 to +0.3
–20 to +75
–55 to +125
Unit
V
V
V
V
V
V
V
°C
°C
Note: The voltages V0, V2, V3, and V5 must obey the relationships VEEn ≥ V0 ≥ V2 ≥ VEE – 7, and 7 ≥ V3 ≥ V5 ≥ VSSn. (Unit: V)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
O3096HA (OT)/43096HA (OT) No. 5280-1/9
1 page  
LC4101C
Pin Functions
Symbol
OUT1 to
OUT240
V0
V2
V3
V5
VEE1/VEE2
VSS1/VSS2
DISP
DF
EIO1
EIO2
CP
LOAD
BS
L/R
I/O
LCD drive outputs
DF
Data
DISP
111
101
O001
011
**0
Note: * don’t care (0 or 1).
OUTn
V0
V2
V3
V5
V5
Function
I V0 level drive voltage input
I
I
V2 level drive voltage input
V3 level drive voltage input
All pins with the same name must be set to the same potential.
I V5 level drive voltage input
– High-voltage block power supply. VEE1 and VEE2 must have the same potential.
– High-voltage block ground. VSS1 and VSS2 must have the same potential.
I All outputs will be held at a fixed V5 level when this pin is low.
I Alternation input
Enable inputs and outputs
L/R
EIO1
EIO2
I/O L In Out
I/O H Out In
Enable inputs: Tie the first stage enable input to VSS, and then connect the enable input of each following stage to the enable
output of the preceding stage.
Enable outputs: When connecting multiple chips in cascade, connect the enable output to the enable input of the next stage.
I Data acquisition clock (falling edge)
I Data load clock (falling edge)
I 4-bit/8-bit switching signal; high: 8 bits, low: 4 bits
8×30: Data latch (BS = high)
L/R CP:
1
2
3
4 29
D7 1
9 17 25 • • • 225
D6 2 10 18 26 • • • 226
D5 3 11 19 27 • • • 227
D4
L
D3
4 12 20 28 • • • 228
5 13 21 29 • • • 229
D2 6 14 22 30 • • • 230
D1 7 15 23 31 • • • 231
I D0 8 16 24 32 • • • 232
D7 240 232 224 216 • • • 16
D6 239 231 223 215 • • • 15
D5 238 230 222 214 • • • 14
D4 237 229 221 213 • • • 13
H
D3 236 228 220 212 • • • 12
D2 235 227 219 211 • • • 11
D1 234 226 218 210 • • • 10
D0 233 225 217 209 • • • 9
Note: The numbers 1 to 240 in the table indicate OUT output numbers.
30
233
234
235
236
237
238
239
240
8
7
6
5
4
3
2
1
Continued on next page.
No. 5280-5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet LC4101C.PDF ] | |
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