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PDF LC371100SM-20LV Data sheet ( Hoja de datos )

Número de pieza LC371100SM-20LV
Descripción 1 MEG (131072 words x 8 bits) Mask ROM Internal Clocked Silicon Gate
Fabricantes Sanyo 
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Ordering number : EN*5087C
Preliminary
CMOS LSI
LC371100SP, SM, ST-10/20LV
1 MEG (131072 words× 8 bits) Mask ROM
Internal Clocked Silicon Gate
Overview
The LC371100SP, LC371100SM and LC371100ST are
131,072-word × 8-bit organization (1,048,576-bit) mask
programmable read only memories.
The LC371100SP-10, LC371100SM-10 and
LC371100ST-10 feature an access time of 100 ns, an OE
access time of 40 ns, and a standby current of 30 µA, and
are optimal for use in 5-V systems that require high-speed
access.
The LC371100SP-20LV, LC371100SM-20LV and
LC371100ST-20LV feature an access time of 200 ns, an
OE access time of 80 ns, and a standby current of 4 µA.
Additionally, they provide high-speed access in 3.3-V
systems (3.0 to 3.6 V) with a 150-ns access time and a 60-
ns OE access time.
These ROMs adopt the JEDEC standard pin assignment
which allows them to replace EPROM easily. To prevent
bus line collisions in multi-bus microcontroller systems,
pin 24 can be mask programmed to be either active high or
active low.
Package Dimensions
unit: mm
3192-DIP32
[LC371100SP]
unit: mm
3205-SOP32
[LC371100SM]
SANYO: DIP32
Features
• 131072 words × 8 bits organization
• Power supply
LC371100SP, SM, ST-10: 5.0 V ± 10%
LC371100SP, SM, ST-20LV: 2.7 to 3.6 V
• Fast access time (tAA, tCA)
LC371100SP, SM, ST-10: 100 ns (max.)
LC371100SP, SM, ST-20LV: 200 ns (max.)
• Operating current
150 ns (VCC = 3.0 to 3.6 V)
LC371100SP, SM, ST-10: 70 mA (max.)
LC371100SP, SM, ST-20LV: 20 mA (max.)
• Standby current
LC371100SP, SM, ST-10: 30 µA (max.)
LC371100SP, SM, ST-20LV: 5 µA (max.)
• Full static operation (internal clocked type)
• Fully TTL compatible (5 V supply)
• 3 state outputs
• JEDEC standard pin configuration
• Package type
LC371100SP-10/20LV: DIP32 (600 mil)
LC371100SM-10/20LV:SOP32 (525 mil)
LC371100ST-10/20LV: TSOP32 (8 mm × 20 mm)
unit: mm
3224-TSOP32
SANYO: SOP32
[LC371100ST]
SANYO: TSOP32 (type-I)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
43098HA (OT)/51195TH (OT)/41095TH (OT) No. 5087-1/5

1 page




LC371100SM-20LV pdf
Timing Chart
LC371100SP, SM, ST-10/20LV
System Design Notes
These LSIs adopt an internal synchronization technique in which operation is started by detecting changes in either the
CE input or the address inputs. As a result, the output data immediately after power on is invalid. Once power has been
applied, valid data is output after the application changes the value of either the CE input or at least one of the address
inputs.
Another point due to the use of the ATD technique is that these LSIs are extremely sensitive to input noise. Applications
must take precautions to provide stable input signals, both for the CE input and the address inputs, to prevent incorrect
operation.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of April, 1998. Specifications and information herein are subject to change
without notice.
PS No. 5087-5/5

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