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PDF LC11011-141 Datasheet ( Hoja de datos )

Número de pieza LC11011-141
Descripción Computer Image Signal Processing Full-Color Gray-Scale Processor
Fabricantes Sanyo 
Logotipo Sanyo Logotipo

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LC11011-141 Hoja de datos, Descripción, Manual
Ordering number : EN*5041A
Preliminaly
CMOS LSI
LC11011-141
Computer Image Signal Processing
Full-Color Gray-Scale Processor
Overview
The LC11011-141 is a pseudo gray scale processor for
TFT LCD. It allows LCD panels with inputs of three to six
bits per RGB to display the equivalent of 16.7 million
colors.
Features
• Handles 8-bits of input data (256-scale data) for each of
the RGB colors.
• Operating mode selection of three, four, or six bit driver
outputs
• Realizes reduced resolution loss (as compared to
dithering techniques) by using intra- and inter-frame
error diffusion processing.
• Supports both 5 V and low voltage (3.3 V) operation.
• Operates with arbitrary clock frequencies up to 50 MHz
(at 5 V) or up to 30 MHz (at 3.3 V).
• Can operate independently of the number of displayed
pixels since internal operation is controlled by the
horizontal and vertical synchronization signals.
Package Dimensions
unit: mm
3151-QFP100E
[LC11011-141]
SANYO: QFP100E
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input and output voltages
Operating temperature
Storage temperature
Symbol
VDD max
VI, VO
Topr
Tstg
Conditions
Electrical Characteristics: At an operating voltage of 5.0 V
Operating Ranges at Ta = 0 to +70°C
Parameter
Supply voltage
Input voltage
Clock frequency
Symbol
VDD
VIN
fclk
Conditions
min
4.5
0
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
0 to +70
–40 to +125
Unit
V
V
°C
°C
Ratings
typ
5.0
Unit
max
5.5 V
VDD
V
50 MHz
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22896HA (OT)/No. 5041-1/7

1 page

LC11011-141 pdf
LC11011-141
Pin Functions
Symbol
VDD
VSS
NC
Pin No.
5, 21, 28, 32, 41,
61, 68, 91
10, 15, 20, 26, 30,
34, 35, 40, 46,51,
56, 66, 71, 73, 82,
87, 90, 98
24, 76, 77
I/O
Input
Input
Power supply (+5 V)
GND (0 V)
Must be left open.
Function
MODESEL0
Mode selection signals [0:3] for the gray scale mode.
The setting process for the mode selection lines is described below.
MODESEL0 is the LSB, and MODESEL3 is the MSB.
1 Input Note that modes 8, 9, C, D and E are compatible with the LC1001-131 (a product that handles 6-bits
of input for each of the RGB signals).
MODESEL1
MODESEL2
Color scale mode
0 1 2 3 4 5 6 7 8 9 AB C DEF
MODESEL0
LH LH LH LH LH LH L HLH
MODESEL1
L L HH L L HH L L HH L L HH
MODESEL2
L L L L HH HH L L L L H HHH
MODESEL3
L L L L L L L L HH HH H HHH
2 Input
Intra-frame
processing Y Y Y Y Y Y Y Y
Y YY
Processing
RR
RR
R
Inter-frame
processing Y Y Y N N N Y Y
N NN
Number of valid input bits 8 8 8 8 8 8 6 6
6 66
Number of output bits
34
6
4 56 34
3 45
Note: Y = yes, N = no, R = reserved
3 Input
MODESEL3
Gray scale modes 0, 8 and C Operating mode for TFT-LCD modules using 3-bit source drivers.
Gray scale modes 1 and 9
Operating mode for TFT-LCD modules using 4-bit source drivers.
Gray scale mode 3
Operating mode for TFT-LCD modules using 6-bit source drivers.
Gray scale modes 5 and D
Operating mode for TFT-LCD modules that perform
FRC or other inter-frame processing.
Operating mode for TFT-LCD modules that perform FRC or other
4
Input
Gray scale modes 6, 7 and E inter-frame processing.
Note: Do not use gray scale modes 0, 1, 3, 8 and 9 with LCD modules that perform FRC or other inter-
frame processing.
BYPASS
TEST0
TEST1
TEST2
TEST3
SCLK
SRDATA [0:7]
SGDATA [0:7]
SBDATA [0:7]
Shsync
Svsync
SHDEN
SCTL0
SCTL1
CLKSEL
CLK
CLKB
100
6
7
8
9
67
57 to 60, 62 to 65
78 to 81, 83 to 86
88, 89, 92 to 97
69
70
72
74
75
99
31
33
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input bypass pin. When this pin is low, the LC11011-141 performs no gray scale processing, but rather
simply passes the input signals through unchanged. When a low level input on this pin is sampled on the
rising edge of the clock, the IC will begin the output of unchanged data two clock cycles later.
Test pins [0:3]; left open in normal operation.
Display dot clock input. Data is processed according to this clock signal.
Input pins for red, green and blue scale data. SRDATA7, SGDATA7, and SBDATA7 are the MSBs.
SRDATA0, SGDATA0, and SBDATA0 are the LSBs.
Horizontal and vertical synchronization signal inputs. These are the sources for the Hsync and Vsync
signals. These are also used to control data processing. These are low level active signals.
Horizontal data valid period signal input. Set this pin high during periods when the horizontal data is
valid. If this signal is not used, tie it high, and set the input data to zero during the horizontal blanking
period.
LCD control inputs. Input control signals that must be matched to the data signal timing. These are the
sources for the CTL signals. If the CTL [0:1] signals are not used, there is no need to input the
SCTL [0:1] signals.
CLKSEL is the dot clock output selection. It is used to select the output mode of the dot clock signal
output pin.
If CLKSEL is low: A signal with the same phase as the SCLK pin is output from the CLK pin.
If CLKSEL is high: A signal with the opposite phase from the SCLK pin is output from the CLKB pin.
Continued on next page.
No. 5041-5/7

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