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PDF LB1876 Datasheet ( Hoja de datos )

Número de pieza LB1876
Descripción Three-Phase Brushless Motor Driver for Polygon Mirror Motors
Fabricantes Sanyo 
Logotipo Sanyo Logotipo

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LB1876 Hoja de datos, Descripción, Manual
Ordering number : ENN6201A
Monolithic Digital IC
LB1876
Three-Phase Brushless Motor Driver
for Polygon Mirror Motors
Overview
The LB1876 is a driver for polygon mirror motors such as
used in laser printers and similar equipment.
It incorporates all necessary circuitry (speed control +
driver) on a single chip. Direct PWM drive enables drive
with low power loss.
Functions and Features
• Three-phase bipolar drive
• Direct PWM drive technique
• Built-in lower side output diode
• Output current limiter
• Reference clock input circuit (FG frequency equivalent)
• PLL speed control circuit
• Phase lock detector output (with masking function)
• Built-in protection circuitry includes current limiter,
restraint protection, overheat protection, low-voltage
protection, etc.
• Brake method switching circuit (free-run or reverse
torque)
• 5V regulator output
• Power save function
Package Dimensions
unit: mm
3235A-HSOP36
[LB1876]
17.8
(6.2)
2.7
36
1
(0.5)
0.8 2.0
0.3
0.25
SANYO: HSOP36
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage 1
Maximum output current
Allowable power dissipation 1
Allowable power dissipation 2
Operating temperature
Storage temperature
Symbol
VCC max
IO max
Pd max1
Pd max2
Topr
Tstg
T 500 ms
IC only
*With substrate
* Substrate: 114.3 × 76.1 × 1.6 mm3, glass epoxy
Conditions
Ratings
30
2.5
0.9
2.1
–20 to +80
–55 to +150
Unit
V
A
W
W
°C
°C
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
61202RM (OT)/62599RM (KI) No. 6201-1/14

1 page

LB1876 pdf
Pin Description
Pin name
OUT1
OUT2
OUT3
IN1+, IN1–
IN2+, IN2–
IN3+, IN3–
FG IN+
FG IN–
GND1
GND2
PWM
FC
FGFIL
Pin number
2
1
36
8, 9
6, 7
4, 5
10
11
12
13
14
15
16
CSD
17
PH
TOC
EO
EI
PD
CLD
FGS
LD
S/S
CLK
VM1
VM2
VCC
VREG
LDSEL
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
BRSEL
GND3
33
34
FRAME
NC 3, 35
LB1876
Function
Output pins.
PWM controls duty cycle ratio by lower transistors.
Connect Schottky diode between these pins and VCC.
Hall input pins for each phase.
Logic High indicates VIN+ > VIN–.
FG comparator non-inverting input.
FG comparator inverting input.
Control circuit ground.
Sub-ground.
PWM oscillation frequency setting pin. Connect to ground via capacitor.
Current control circuit frequency characteristics compensation pin. Connect to ground via capacitor.
FG filter pin. Connect to ground via capacitor if noise in FG signal is a problem.
Restraint protection circuit operating time setting pin/reset pulse setting pin.
Connect to ground via capacitor. If the protection circuit is not to be used, connect a resistor in parallel
with capacitor.
RF waveform smoothing pin. Connect to ground via capacitor.
Torque specifying input pin. Normally connected to EO pin. When TOC potential falls, ON duty cycle ratio of
lower side output transistors changes and torque increases.
Error amplifier output.
Error amplifier input.
Phase comparator output pin. Phase deviation is output as a duty cycle change of the pulse.
Phase lock signal masking time setting pin. Connect to ground via capacitor. Leave open if masking is not
required.
FG Schmitt output (open collector output).
Phase lock detector output (open collector output). Goes ON when PLL is locked.
Start/stop input. Low: Start; High or Open: Stop.
Clock input. 10 kHz max.
Output block power supply. Short to VM2 for use.
Output current detector pin. Connect to VCC via low resistor.
Set to maximum output current IOUT = 0.5/Rf.
Power supply pin. Connect to ground via capacitor to prevent noise.
5V regulator output pin (control circuit power supply). Connect to ground via capacitor to stabilize operation.
Phase lock signal masking switching pin. When "Low", the unlock signal (short "High" signal of LD output) is
masked. When "High" or Open, the lock signal (short "Low" signal of LD output) is masked.
Braking method select pin. "Low" selects reverse torque control and "High" or Open selects free-run.
When reverse torque is controlled, lower side output transistors require external SBD.
Output circuit ground.
The FRAME pin is connected internally to the metal frame at the base of the IC. Electrically, both the FRAME
pin and the metal frame are left open. To improve thermal dissipation, provide a corresponding land on the
PCB and solder the FRAME pin to that land.
Not connected internally. Can be used for wiring.
No. 6201-5/14

5 Page

LB1876 arduino
Continued from preceding page.
Pin No.
Symbol
LB1876
Description
Phase lock signal mask switching
Low: 0 to 1.5 V
High: 3.5 V to VREG
When open, this pin goes to the high level.
32 LDSEL
When low, transient unlock signals (short
high-level periods on the LD output) are
masked, and when high, transient lock
signals (short low-level periods on the LD
output) are masked.
VREG
Equivalent circuit
30 k
2k
32
Braking control
Low: 0 to 1.5 V
High: 3.5 V to VREG
When open, this pin goes to the high level.
33 BRSEL
When low, reverse torque control is applied
and when high, the circuit operates in free-
running mode. An external Schottky barrier
diode is required on the low side output when
reverse torque control is applied.
FREME
This pin must be left open.
VREG
30 k
2k
33
No. 6201-11/14

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