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PDF LB1875 Data sheet ( Hoja de datos )

Número de pieza LB1875
Descripción Polygon Mirror Motor Predriver IC
Fabricantes Sanyo 
Logotipo Sanyo Logotipo



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Ordering number : EN6002
LB1875
Monolithic Digital IC
LB1875
Polygon Mirror Motor Predriver IC
Overview
The LB1875 is a predriver IC for polygon mirror
motors. By using a driver array or discrete transis-
tors (FETs) at the output, motor drive with high
rotation precision is possible. PAM drive or direct
PWM drive can be selected for the output to realize
high-efficiency control with minimum power loss.
Package Dimensions
unit: mm
3235-HSOP36
[LB1875]
17.9
6.2
2.7
36
Features
• Three-phase bipolar drive
• Direct PWM drive (bottom side) or PAM drive selectable
• PLL speed control circuit
• PWM oscillator
• Quartz oscillator
• Frequency divider
• FG with Schmitt comparator
• FG input single edge, dual edge selector circuit
• Integrating amplifier
• Phase lock detector output
• Current limiter
• Motor lock protection
• Thermal protection
• Forward/reverse circuit
• 5V regulator output
1
0.55
0.8 0.3
0.25
SANYO : HSOP36
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D0898RM(KI) No. 6002-1/17

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LB1875 pdf
Continued from previous page
Parameter
[CLKSEL pin]
High level input voltage
Middle level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
[LIM pin]
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
Symbol
VIH(CSEL)
VIM(CSEL)
VIL(CSEL)
VIO(CSEL)
IIH(CSEL) VCSEL=VREG
IIL(CSEL) VCSEL=0V
VIH(LIM)
VIL(LIM)
VIO(LIM)
IIH(LIM) VLIM=VREG
IIL(LIM) VLIM=0V
LB1875
Conditions
Ratings
min typ max
Unit
4.0
2.0
0
VREG–0.5
–10
–200
0
–140
VREG
3.0
1.0
VREG
+10
V
V
V
V
µA
µA
3.5
0
VREG–0.5
–10
–200
0
–140
VREG
1.5
VREG
+10
V
V
V
µA
µA
3-phase logic truth table (IN = “H” indicates the IN+ > INcondition)
F/R= "L"
F/R= "H"
Output
IN1 IN2 IN3 IN1 IN2 IN3 SOURCE SYNC
1H L H L H L
VH
UL
2H
L
L
LHH
WH
UL
3 H H L L L H WH
VL
4L H L H L H
UH
VL
5L HHH L L
UH
WL
6L L HHH L
VH
WL
S/S pin
Input state
High or open
L
Condition
Stop
Start
FGSEL pin
Input state
High or open
L
Edge detection
FG dual edge
FG single edge
LIM pin
Input state
High or open
L
Output pin (UH, VH, WH)
No PWM (PAM operation)
PWM (direct PWN operation)
PWMOUT pin
PWM output
FG/Schmitt comparator output
CLKSEL pin
Input state
High or open
M
L
Divisor
1024 x 4
1024
1024 x 3
Pin Assignment
36 35 34 33 32 31 30 29 28
27 26 25 24 23 22 21 20 19
LB1875
123456789
10 11 12 13 14 15 16 17 18
A11348
No. 6002-5/17

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LB1875 arduino
LB1875
7. PWM frequency
The PWM frequency is determined by the capacitance connected to the C pin.
f PWM =.. 1/(15000 x C)
PWM
The PWM frequency should be between 15 and 50 kHz. If the frequency is too low, noise and control performance may be a
problem. If it is too high, switching losses will increase.
8. LD output
The LD1 output is ON when phase lock is achieved. Phase lock is evaluated only by the phase (through edge comparison), not by
speed deviation. Therefore when LD1 is ON, speed deviation is affected by the FG signal acceleration for example when establishing
the lock condition. (The lower the acceleration, the lower the speed deviation.) When it is necessary to limit speed deviation when
LD1 is ON, the results of actual motor speed measurement must be applied.
9. Power supply
When using FETs as bottom-side output transistors, applying a voltage of 12V to the V pin makes it possible to supply a gate
CC
voltage of about 10V. When using FETs or bipolar transistors that can handle a low gate voltage, the V and V pins can also be
CC REG
short- circuited to apply 5V. (In this case, do not apply voltage higher than 5.5V.)
Since this IC is designed for use in high-current motors, the power supply line may fluctuate easily. Therefore a capacitor of
sufficient capacitance must be provided between the VCC pin and ground, to assure stable operation. If a diode is used in the power
line for reverse-connection protection, power line fluctuations may be further increased, which will require more capacitance.
10. Motor lock protection circuit
To protect the IC and the motor itself when rotation is inhibited, a motor lock protection circuit is provided. If the LD output is High
(unlocked) for a certain interval in the start condition, the external bottom-side transistors are turned off. The length of the interval
is determined by the capacitance at the CSD pin. A capacitance of 0.1 µF results in a trigger interval of about 10 seconds.
Trigger interval (S) =.. 110 x C (µF)
The trigger interval should be set so as to leave sufficient leeway for motor startup. Speed reduction due to clock frequency switching
does not trigger the protection circuit.
When the protection circuit has been triggered, the condition can only be canceled by setting the system to the stop condition or by
turning the power off and on again. When wishing not to use the motor lock protection circuit, connect the CSD pin to ground.
11. Low voltage protection circuit
The low voltage protection circuit cuts off the bottom-side output transistors (external) when the voltage at the VREG pin falls below
3.75V (typ.). The circuit action is released when the voltage rises above approx. 4.0V (typ.).
12. F/R switching
Forward/reverse switching in principle should be carried out while the motor is stopped. If switching is carried out while the motor
is running, feedthrough current (due to output transistor delay) is prevented by the circuit design, but a high current will flow in the
output transistors (due to counterelectromotive voltage and coil resistance). If such a condition is anticipated, the output transistors
must be selected appropriately, to allow handling even higher current than in normal use.
13. Soft start
In PAM drive mode, connecting a capacitor (approx. 0.01 to 0.1 µF) between the SOFT pin and ground enables soft start (gradual
increase in PWM ON duty cycle, causing a sloped rise in motor supply voltage). This prevents the current flow exceeding the set
current due to switching regulator circuit delay at startup. The Soft start function is active only immediately after motor startup.
When the motor is stopped, the output transistors are turned off, therefore the charge accumulated in the switching regulator smoothing
capacitors can only be discharged as leak current of the output transistors. When the motor is restarted before the supply voltage has
dropped, the soft start function will not be active. Therefore it is necessary to discharge the capacitors via a resistor so that the soft
start function operates properly.
No. 6002-11/17

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