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PDF KB8823 Data sheet ( Hoja de datos )

Número de pieza KB8823
Descripción FREQUENCY SYNTHESIZER
Fabricantes Samsung 
Logotipo Samsung Logotipo



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No Preview Available ! KB8823 Hoja de datos, Descripción, Manual

PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
INTRODUCTION
The KB8821/22/23 are high performance dual frequency syn-
thesizers with integrated prescalers designed for RF operation
20-TSSOP-225
up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz.
The KB8821/22/23 contain dual-modulus prescalers. The RF
synthesizer adopts a 64/65 or an 128/129 prescaler(32/33 or
64/65 for the KB8823) and the IF synthesizer adopts an 8/9 or
a 16/17 prescaler.
Using a proprietary digital phase-locked-loop technique, the
KB8821/22/23 have linear phase detector characteristic and
can be used for very stable, low noise local oscillator signal.
Supply voltage can range from 2.7V to 4.0V. The KB8821/22/
23 are now available in a 20-TSSOP/24-QFN package.
ORDERING INFORMATION
FEATURES
Device
Package Tem. Range
• Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA)
• Operating voltage range : 2.7 ~ 4.0V
• Selectable power saving mode(Icc=1uA typical @3V)
• Dual modulus prescaler :
KB8821/22
(RF) 64/65 or 128/129
KB8823
KB8821/22/23
(RF) 32/33 or 64/65
(IF) 8/9 or 16/17
• Programmability via serial bus interface
• No dead-zone PFD
• Variable charge pump output current
• High speed lock mode
KB8821/22/23 20-TSSOP-225 -40 ~ +85°C
KB8821/22/23
24-QFN* -40 ~ +85°C
* QFN : Quad Flat Non-leaded(see Addendum).
APPLICATIONS
• Cellular telephone systems : KB8821
• Portable wireless communications : KB8822
(PCS/PCN, cordless)
• Wireless Local Area Networks (W-LANs)
: KB8823
• Other wireless communication systems
BLOCK DIAGRAM
finRF
finRF
+
-
CLOCK
LE
DATA
OSCin
finIF
finIF
+
-
RF
Prescaler
RF
N Counter
Serial Data Control
RF
R Counter
IF
R Counter
IF
Prescaler
IF
N Counter
RF
Phase
Detector
RF CPoRF
Charge
Pump
RF
LD
foLD
Data Out
Multiplexer
foLD
IF
Phase
Detector
IF
LD
IF
Charge
CPoIF
Pump
Figure 1. BLOCK DIAGRAM
99-06-15
1

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KB8823 pdf
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
EQUIVALENT CIRCUIT DIAGRAM
CLOCK, DATA, LE
foLD
KB8821/22/23
OSCin
CPoRF, CPoIF
finRF, finRF, finIF, finIF
finRF,
finIF
Vbias
99-06-15
finRF,
finIF
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KB8823 arduino
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION- Continued
Control Bits
Control Bits
C1 C2
00
01
10
11
KB8821/22/23
DATA Location
IF R Counter
RF R Counter
IF N Counter
RF N Counter
Programmable Reference Counter(IF / RF R Counter)
If the Control Bits are 00(IF) or 01(RF), data is moved from the 20-bit shift register into the R-latch which sets
the reference counter. Serial data format is shown in the table below.
LSB MSB
C1 C2 R R R R R R R R R R R R R R R R R R R R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Division Ratio of the R Counter, R
Control Bits
15-Bit Programmable Reference Counter Ratio
Program Modes
Division R R R R R R R R R R R R R R R
Ratio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3 000000000000011
4 000000000000100
• •••••••••••••••
32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Division ratio : 3 to 32767
Data are shifted in MSB first
99-06-15
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