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PDF K9XXG08UXM-E Data sheet ( Hoja de datos )

Número de pieza K9XXG08UXM-E
Descripción 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
Fabricantes Samsung 
Logotipo Samsung Logotipo



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No Preview Available ! K9XXG08UXM-E Hoja de datos, Descripción, Manual

K9W4G08U1M K9W4G16U1M
K9K2G08Q0M K9K2G16Q0M
K9K2G08U0M K9K2G16U0M
Document Title
256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0 1. Initial issue
0.1 1. IOL(R/B) of 1.8V device is changed.
-min. Value: 7mA -->3mA
-typ. Value: 8mA -->4mA
0.2 1. 5th cycle of ID is changed
: 40h --> 44h
0.3 1. Add WSOP Package Dimensions.
0.4 1. Add two-K9K2GXXU0M-YCB0/YIB0 Stacked Package
0.5 1. Min valid block of K9W4GXXU1M-YCB0/YIB0 is changed .
- min. 4016 --> 4036
0.6 1. Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 30
invalid blocks.
2. K9W4GXXU1M’s ID is changed
(Before)
Device 2nd Cycle 3rd cycle 4th Cycle 5th Cycle
K9W4G08U1M DCh C3 15h 4Ch
K9W4G16U1M CCh C3 55h 4Ch
(After)
Device 2nd Cycle 3rd cycle 4th Cycle 5th Cycle
K9W4G08U1M DAh C1 15h 44h
K9W4G16U1M CAh C1 55h 44h
Draft Date Remark
Aug. 30.2001 Advance
Nov. 5.2001
Jan. 23. 2002
May.29.2002
Aug.13.2002
Aug. 22.2002
Nov. 07.2002
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 36)
0.7 2. Add the data protection Vcc guidence for 1.8V device - below about 1.1V. Nov. 22.2002
(Page 37)
0.8 The min. Vcc value 1.8V devices is changed.
K9K2GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 6.2003
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
1

1 page




K9XXG08UXM-E pdf
K9W4G08U1M K9W4G16U1M
K9K2G08Q0M K9K2G16Q0M
K9K2G08U0M K9K2G16U0M
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9K2G08U0M-VCB0,FCB0/VIB0,FIB0
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 N.C
47 N.C
46 DNU
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 DNU
38 N.C
37 Vcc
36 Vss
35 N.C
34 DNU
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 DNU
26 N.C
25 N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
15.40±0.10
0.70 MAX
0.58±0.04
#1 #48
#24 #25
(0.1Min)
17.00±0.20
5
0.45~0.75

5 Page





K9XXG08UXM-E arduino
K9W4G08U1M K9W4G16U1M
K9K2G08Q0M K9K2G16Q0M
K9K2G08U0M K9K2G16U0M
FLASH MEMORY
Product Introduction
The K9K2GXXX0M is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8(X8 device) or
1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or
1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056-
word(X16 device) cache register are serially connected to each other. Those serially connected registers are connected to memory
cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program opera-
tions. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a
different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells
reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 2048 separately erasable 128K-byte(X8 device) or 64K-word(X16 device) blocks. It indicates
that the bit by bit erase operation is prohibited on the K9K2GXXX0M.
The K9K2GXXX0M has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). This scheme dramatically reduces pin
counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-
mands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other
commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execu-
tion. The 256M byte(X8 device) or 128M word(X16 device) physical space requires 29(X8) or 28(X16) addresses, thereby requiring
four cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need
the same four address cycles following the required command input. In Block Erase operation, however, only the two row address
cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific
commands of the K9K2GXXX0M.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address
input after power-on.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
1st. Cycle
Read
00h
Read for Copy Back
00h
Read ID
90h
Reset
FFh
Page Program
80h
Cache Program
80h
Copy-Back Program
85h
Block Erase
60h
Random Data Input*
85h
Random Data Output*
05h
Read Status
70h
NOTE : 1. Random Data Input/Output can be executed in a page.
2nd. Cycle
30h
35h
-
-
10h
15h
10h
D0h
-
E0h
Acceptable Command during Busy
O
O
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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