PDF K4J55323QF-GC16 Data sheet ( Hoja de datos )

Número de pieza	K4J55323QF-GC16
Descripción	256Mbit GDDR3 SDRAM
Fabricantes	Samsung
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No Preview Available ! K4J55323QF-GC 256M GDDR3 SDRAM 256Mbit GDDR3 SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM with Uni-directional Data Strobe and DLL (144 - Ball FBGA) Revision 1.7 January 2005 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev 1.7 (Jan. 2005) 1 page K4J55323QF-GC PIN CONFIGURATION Normal Package (Top View) 256M GDDR3 SDRAM 234 B WDQS0 RDQS0 VSSQ 5 DQ3 6 DQ2 7 DQ0 8 DQ31 9 DQ29 10 DQ28 11 12 13 VSSQ RDQS3 WDQS3 C DQ4 DM0 VDDQ VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ VDDQ DM3 DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 RFU3 VDD F DQ17 DQ16 VDDQ G DQ19 DQ18 VDDQ H WDQS2 RDQS2 VDDQ J DQ20 DM2 VDDQ K DQ21 DQ22 VDDQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VDD RFU4 DQ24 VDDQ DQ15 DQ14 VDDQ DQ13 DQ12 VDDQ RDQS1 WDQS1 VDDQ DM1 DQ11 VDDQ DQ9 DQ10 L DQ23 M VREF A3 A2 VDD A10 VSS RFU2 VDD /RAS RESET CKE VDD RFU5 RFU1 ZQ VSS /CS VDD A9 A4 DQ8 A5 VREF N A0 A1 A11 BA0 /CAS CK /CK /WE BA1 A8/AP A6 A7 NOTE : 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. (M,13) VREF for CMD and ADDRESS 4. (M,2) VREF for Data input -5- Rev 1.7 (Jan. 2005) 5 Page K4J55323QF-GC 256M GDDR3 SDRAM PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss. The value of the resistor must be six times the desired output impedance. For example, a 240Ω resistor is required for an output impedance of 40Ω. To ensure that output impedance is one sixth the value of RQ (within 10 %), the range of RQ is 120Ω to 360Ω (20Ω to 60Ω output impedance). RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1% resisters. The output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in progress to compen- sate for variations in supply voltage and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all data sheet timing and current specifications are met during an update. To guarantee optimum out- put driver impedance after power-up, the GDDR3(x32) needs 20us after the clock is applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 20us, but optimal output impedance is not guaranteed. The value of ZQ is also used to calibrated the internal address/command termination resisters. The two termination values that are selectable at power up are 1/ 2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The two termination values that are select- able are 1/4 of ZQ and 1/2 of ZQ. BURST LENGTH Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE com- mand. Burst length of 4 only is available. Reserved states should not be used, as unknown operation or incompatibility with future ver- sions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when the burst length is set to four (Where Ai is the most significant column address bit for a given config- 0 uration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmable burst length applies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit A3. This device does not support the interleaved burst mode found in DDR SDRAM devices. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition Burst Length 4 Burst Definition Starting Column Address A1 A0 00 Order of Access within A burst Type= Sequential 0-1-2-3 NOTE : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero - 11 - Rev 1.7 (Jan. 2005) 11 Page

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