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PDF K4F170412D Data sheet ( Hoja de datos )

Número de pieza K4F170412D
Descripción 4M x 4Bit CMOS Dynamic RAM with Fast Page Mode
Fabricantes Samsung 
Logotipo Samsung Logotipo



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No Preview Available ! K4F170412D Hoja de datos, Descripción, Manual

K4F170411D, K4F160411D
K4F170412D, K4F160412D
CMOS DRAM
4M x 4Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power con-
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 4Mx4 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for high level computer, microcomputer and personal computer.
FEATURES
• Part Identification
- K4F170411D-B(F) (5V, 4K Ref.)
- K4F160411D-B(F) (5V, 2K Ref.)
- K4F170412D-B(F) (3.3V, 4K Ref.)
- K4F160412D-B(F) (3.3V, 2K Ref.)
Active Power Dissipation
Speed
-50
-60
3.3V
4K 2K
324 396
288 360
Unit : mW
5V
4K 2K
495 605
440 550
Refresh Cycles
Part
VCC
NO.
K4F170411D 5V
K4F170412D
K4F160411D
K4F160412D
3.3V
5V
3.3V
Refresh
cycle
4K
2K
Refresh period
Normal L-ver
64ms
32ms
128ms
Performance Range
Speed tRAC
-50 50ns
tCAC
13ns
-60 60ns 15ns
tRC
90ns
110ns
tPC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
A0-A11
(A0 - A10)*1
A0 - A9
(A0 - A10)*1
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
4,194,304 x 4
Cells
Column Decoder
Vcc
Vss
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

1 page




K4F170412D pdf
K4F170411D, K4F160411D
K4F170412D, K4F160412D
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Symbol
Input capacitance [A0 ~ A11]
CIN1
Input capacitance [RAS, CAS, W, OE]
CIN2
Output capacitance [DQ0 - DQ3]
CDQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS (0°CTA70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
-50
Min Max
90
133
50
13
25
0
0 13
3 50
30
50 10K
13
50
13 10K
20 37
15 25
5
0
10
0
10
25
0
0
0
10
10
13
13
-60
Min Max
110
155
60
15
30
0
0 15
3 50
40
60 10K
15
60
15 10K
20 45
15 30
5
0
10
0
10
30
0
0
0
10
10
15
15
Units Notes
ns
ns
ns 3,4,10
ns 3,4,5
ns 3,10
ns 3
ns 6
ns 2
ns
ns
ns
ns
ns
ns 4
ns 10
ns
ns
ns
ns
ns
ns
ns
ns 8
ns 8
ns
ns
ns
ns

5 Page





K4F170412D arduino
K4F170411D, K4F160411D
K4F170412D, K4F160412D
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ3(7)
VIH -
VIL -
tRAS
tRC
tCRP
tRCD
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tCSH
tRSH
tCAS
tCAH
COLUMN
ADDRESS
tRAL
tCWL
tRWL
tWP
tOED
tOEH
tDS tDH
DATA-IN
CMOS DRAM
tRP
tCRP
Dont care
Undefined

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