DataSheet.es    


PDF K4C561638C-TCD3 Data sheet ( Hoja de datos )

Número de pieza K4C561638C-TCD3
Descripción 256Mb Network-DRAM
Fabricantes Samsung 
Logotipo Samsung Logotipo



Hay una vista previa y un enlace de descarga de K4C561638C-TCD3 (archivo pdf) en la parte inferior de esta página.


Total 42 Páginas

No Preview Available ! K4C561638C-TCD3 Hoja de datos, Descripción, Manual

K4C5608/1638C
256Mb Network-DRAM
256Mb Network-DRAM Specification
Version 0.7
- 1 - REV. 0.7 Aug. 2003

1 page




K4C561638C-TCD3 pdf
K4C5608/1638C
Pin Names
Pin
A0 to A14
BA0, BA1
DQ0 to DQ7 (x8)
DQ0 to DQ15 (x16)
CS
FN
PD
CK, (CK)
DQS (X8)
UDQS/LDQS (X16)
Vdd
Vss
VddQ
VssQ
VREF
NC1,NC2
Name
Address Input
Bank Address
Data Input/Output
Chip Select
Function Control
Power Down Control
Clock Input
Write/Read Data Strobe
Power(+2.5V)
Ground
Power (+2.5V)
(for I/O buffer)
Ground
(for I/O buffer)
Reference Voltage
No Connection
256Mb Network-DRAM
Pin Assignment (Top View)
K4C561638C-TC
K4C560838C-TC
Vdd Vdd 1
DQ0 DQ0 2
VddQ VddQ
DQ1 NC2
3
4
DQ2 DQ1 5
VssQ VssQ
DQ3 NC2
6
7
DQ4 DQ2
VddQ VddQ
8 400mil Width
9 875mil Length
DQ5 NC2 10
DQ6 DQ3 11
VssQ VssQ 12 66Pin TSOP II
DQ7 NC2 13
NC1 NC1 14
VddQ VddQ 15
LDQS
NC1
Vdd
NC1
NC2
A14
A13
FN
CS
NC1
BA0
BA1
A10
A0
A1
A2
A3
Vdd
NC2
NC1
Vdd
NC1
NC2
A14
A13
FN
CS
NC1
BA0
BA1
A10
A0
A1
A2
A3
Vdd
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
0.65mm
Lead Pitch
66 Vss Vss
65 DQ7 DQ15
64 VssQ VssQ
63 NC2 DQ14
62 DQ6 DQ13
61 VddQ VddQ
60 NC2 DQ12
59 DQ5 DQ11
58 VssQ VssQ
57 NC2 DQ10
56 DQ4 DQ9
55 VddQ VddQ
54 NC2 DQ8
53 NC1 NC1
52 VssQ VssQ
51 DQS UDQS
50 NC1 NC1
49 VREF VREF
48 Vss Vss
47 NC2 NC2
46 CK CK
45 CK CK
44 PD PD
43 NC1 NC1
42 A12 A12
41 A11 A11
40 A9 A9
39 A8 A8
38 A7 A7
37 A6 A6
36 A5 A5
35 A4 A4
34 Vss Vss
- 5 - REV. 0.7 Aug. 2003

5 Page





K4C561638C-TCD3 arduino
K4C5608/1638C
256Mb Network-DRAM
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
Item
D4(400Mbps)
Min Max
DA(366Mbps)
Min Max
D3(333Mbps)
Min Max
Units Notes
tRC Random Cycle Time
25 - 27.5 - 30 -
3
tCK Clock Cycle Time
CL = 3
5.5
7.5
6
7.5 6.5 7.5
CL = 4
5
7.5 5.5 7.5
6
7.5
3
3
tRAC
Random Access Time
- 22 - 24 - 26
3
tCH Clock High Time
0.45*tCK - 0.45*tCK - 0.45*tCK -
3
tCL Clock Low Time
0.45*tCK - 0.45*tCK - 0.45*tCK -
3
tCKQS DQS Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tQSQ
Data Output Skew from DQS
- 0.4 - 0.45 - 0.5
4
tAC Data Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tOH Data Output Hold Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tQSPRE DQS(Read) Preamble Pulse Width
0.9*tCK-0.2 1.1*tCK+0.2 0.9*tCK-0.2 1.1*tCK+0.2 0.9*tCK-0.2 1.1*tCK+0.2
3
tHP CLK half period ( minium of Actual tCH, tCL)
min(tCH, tCL) - min(tCH, tCL) - min(tCH, tCL) -
tQSP
DQS(Read) Pulse Width
tHP-0.55
-
tHP-0.6
- tHP-0.65 -
4
tQSQV Data Output Valid Time from DQS
tHP-0.55
-
tHP-0.6
tHP-0.65
-
4
tDQSS DQS(Write) Low to High Setup Time
0.75*tCK
1.25*tCK
0.75*tCK
1.25*tCK
0.75*tCK
1.25*tCK
3
tDSPRE DQS(Write) Preamble Pulse Width
0.4*tCK - 0.4*tCK - 0.4*tCK -
4
tDSPRES DQS First Input Setup Time
0-0-0-
3
tDSPREH DQS First Low Input Hold Time
0.25*tCK - 0.25*tCK - 0.25*tCK -
3
tDSP
tDSS
DQS High or Low Input Pulse Width
DQS Input Falling Edge to Clock Setup Time
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
4
CL = 3
1.3
-
1.4
-
1.5
- ns 3, 4
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
tDSPST DQS(Write) Postamble Pulse Width
0.45*tCK - 0.45*tCK
0.45*tCK
-
4
tDSPSTH DQS(Write) Postamble Hold Time
CL = 3
1.3
-
1.4
-
1.5
-
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
3, 4
tDSSK UDQS - LDQS Skew (x16)
-0.5*tCK
0.5*tCK
-0.5*tCK
0.5*tCK
-0.5*tCK
0.5*tCK
tDS Data Input Setup Time from DQS
0.5 - 0.5 - 0.6 -
4
tDH Data Input Hold Time from DQS
0.5 - 0.5 - 0.6 -
4
tDIPW Data Input pulse Width (for each device)
1.5 - 1.5 - 1.9 -
tIS Command / Address Input Setup Time
0.9 - 0.9 - 1 -
3
tIH Command / Address Input Hold Time
0.9 - 0.9 - 1 -
3
tIPW
Command / Address Input Pulse Width (for each device)
2.0
-
2.0
-
2.2
-
tLZ Data-out Low Impedance Time from CLK
-0.65 - -0.75 - -0.85 -
3, 6, 8
tHZ Data-out High Impedance Time from CLK
- 0.65 - 0.75 - 0.85
3, 7, 8
tQSLZ DQS-out Low Impedance Time from CLK
-0.65 - -0.75 - -0.85 -
3, 6, 8
tQSHZ DQS-out High Impedance Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 7, 8
tQPDH Last Output to PD High Hold Time
0-0-0-
tPDEX Power Down Exit Time
2-2-2-
3
tT Input Transition Time
0.1 1 0.1 1 0.1 1
tFPDL PD Low Input Window for Self-Refresh Entry
-0.5*tCK 5 -0.5*tCK 5 -0.5*tCK 5
3
- 11 - REV. 0.7 Aug. 2003

11 Page







PáginasTotal 42 Páginas
PDF Descargar[ Datasheet K4C561638C-TCD3.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
K4C561638C-TCD3256Mb Network-DRAMSamsung
Samsung
K4C561638C-TCD4256Mb Network-DRAMSamsung
Samsung
K4C561638C-TCD4000256Mb Network-DRAMSamsung
Samsung
K4C561638C-TCDA256Mb Network-DRAMSamsung
Samsung

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar