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PDF PDSP16515A Data sheet ( Hoja de datos )

Número de pieza PDSP16515A
Descripción Stand Alone FFT Processor
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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No Preview Available ! PDSP16515A Hoja de datos, Descripción, Manual

DS3922
PDSPP1DS6P51165515AA
Stand Alone FFT Processor
Advance Information
Issue 2.0
April 1999
Features
q Completely self contained FFT Processor
q Pin and functionally compatible with the
PDSP16510A
q Expanded width internal RAM supports up to 1024
complex points
q 18 bit internal data bus with block floating point
arithmetic for increased dynamic range
q 500 MIP operation gives 87 microsecond
transformation times for 1024 points
q Up to 45MHz sampling rates with multiple devices.
q Up to 85dB noise rejection
q A choice of internal window operators with no
external ROM provide up to 67dB side lobe
attenuation.
q 84 pin PGA or 132 pin surface mount package
Associated Products
PDSP16330 Pythagoras Processor.
PDSP16256 Programmable FIR Filter.
PDSP16350 I/Q Splitter / NCO
PDSP16510A Stand Alone FFT Processor
The PDSP16515A performs Forward or Inverse Fast
Fourier Transforms on complex or real data sets
containing up to 1024 points. Data and coefficient input
are both represented by 16 bits. Data is expanded
internally to 18 bits and subject to Block Floating Point
arithmetic to preserve a greater dynamic range.
An internal RAM is provided which can hold up to 1024
complex data points. This removes the memory transfer
bottleneck, inherent in building block solutions. Its
organisation allows the PDSP16515A to
simultaneously input new data, transform data stored in
the RAM, and to output previous results. No external
buffering is needed for transforms containing up to 256
points, and the PDSP16515A can be directly connected
to an A/D converter to perform continuous transforms.
The user can choose to overlap data blocks by either
0%, 50%, or 75%. Inputs and outputs are synchronous
to the 45MHz system clock used for internal operations.
Ordering Information
PDSP16515A C0 AC
( Commercial - PGA
Package )
PDSP16515A C0 GC
( Commercial - Leaded
Chip Carrier )
PDSP16515A B0 AC
( Industrial - PGA
Package )
PDSP16515A B0 GC
( Industrial - Leaded
Chip Carrier )
PDSP16515A A0 AC
( Military - PGA
Package )
PDSP16515A A0 GC
( Military - Leaded Chip
Carrier )
PDSP16515A/MA/GCPR ( Military - Screened
Leaded Chip Carrier. See separate datasheet for
details )
A 1024 point complex transform can be completed in
some 87µs, which is equivalent to throughput rates of
500 million operations per second. Multiple devices can
be connected in parallel in order to increase the
sampling rate up to the 45MHz system clock. Six
devices are needed to give the maximum performance
with 1024 point transforms.
Either a Hamming or a Blackman-Harris window
operator can be internally applied to the incoming real or
complex data. The latter gives 67dB side lobe
attenuation. The operator values are calculated
internally and do not require an external ROM nor do
they incur any time penalty.
The increased internal bus size together with block
floating arithmetic produce up to 85dB of noise
rejection.
The device outputs the real and imaginary components
of the frequency bins. These can be directly connected
to the PDSP16330 in order to produce magnitude and
phase values from the complex data.
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PDSP16515A pdf
generated internally, and applied to the incoming real or
complex data with no time penalty. No external ROM is
needed to support these windows. The Blackman-Harris
window gives improved dynamic range over the Hamming
window when two closely spaced frequencies are to be
detected, and one is of smaller magnitude than the other. It
does, however, reduce the actual frequency resolution, and
the Hamming window may then be preferable.
Data in and out of the device is represented by 16 bit real and
imaginary components, with 16 bit sine and cosine values
contained in an internal ROM. Conditional scaling, coupled
with word growth through the butterfly data path, gives
increased dynamic range. Transforms can be computed with
sample sizes of either 256 or 1024 data points. The 256 point
option can alternatively be used to simultaneously execute
either four 64 point transforms, or sixteen 16 point transforms.
The 16 point mode can only be used with a rectangular
window, and no overlapping of data blocks is possible.
The device can be configured, either, to perform continuous
transforms in a real time application, or as slave processor to
a more general purpose signal processing system. In the
continuous mode, with transform sizes of 256 points or less,
it contains three internal control units which simultaneously
allow new data to be loaded, present data to be transformed,
and previous results to be dumped. Additional, external, input/
output buffering is not needed. The internal input buffer also
allows data blocks to be overlapped by either 50% or 75%,
apart from the mode with no overlaps.
When 1024 point transforms are to be calculated, without loss
of incoming data during the transform time, it is necessary to
use an input buffer. This requirementcan be satisfied by an
external buffer memory.
In any of the real or complex modes it is possible to obtain
higher performance by connecting devices in parallel. It is then
possible to increase the sampling rate to that of the system
clock used for internal operations.
The mode of operation of the device is controlled by 16 bits in
a control register. These are loaded through the AUX15:0 port
when a control signal DEF is active low. This port is also used
to provide the imaginary component of complex input data,
and, if complex transforms are to be performed, an external
tristate buffer will be needed to isolate the control information.
This should only be enabled when DEF is active. DEF is also
used to initialise the internal circuitry, and can be a simple
power on reset if control parameters need not be
subsequently changed.
Data Precision
During each pass of a radix-4 fast Fourier transform it is
possible for either component of a particular result to grow by
a factor of up to four in the first pass, and 5.242 in subsequent
passes. This is between two and three bits in each pass and
the data path must allow for this word growth to avoid any
possibility of overflow. At the end of the data path the word is
preserved at 18 bits and stored in the internal RAM. Any un-
necessary word growth to prevent overflow thus results in loss
PDSP16515A
INPUT
SELECT
RAM
SIN / COS
ROM
16
Shift left until largest point
has one sign bit.
18
MULTIPLIER
S S 29 - 14 13 - 0
"1"
18
18
CR
BIT3
FIRST ADDER
19Bit Result
18 - 1 0
REGISTER FILE
SECOND ADDER
19Bit Result
18 - 1 0
REGISTER FILE
THIRD ADDER
19Bit Result
18 - 1
17 - 0
SELECT
Figure. 3 One of Four Data Paths
of arithmetic precision, and has a detrimental effect on the
dynamic range achievable.
In practice these large word growths only occur when bipolar
complex square waves are transformed, and even then will
not occur on every pass. The PDSP16515A compromises by
allowing a 2 bit word growth during the butterfly calculation in
the first pass. This is equivalent to ignoring the most significant
bit of the 19 bit final result, which is assumed to be an extra sign
bit, and then selecting the next 18 bits for storage. In
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PDSP16515A arduino
PDSP16515A
DAV
DEN
DOS
DATA
O/P
S3:0
Dummy Strobes
(1) (2) (3)
TPS
TPW
TPH
(4)
Un-defined
TLZ
TDD
O/P 1
THZ
O/P 1
TOH
Un-defined
Scale Tag Value
In this zone SCLK and DOS requirements have to be met - See "User Notes - stopping DOS"
TVI
O/P 2
Scale Tag Value
O/P N
THZ
Characteristic
Symbol Min Max
Units
DEN Set Up Time
Host Strobe Width
DEN Hold Time
DAV in-active going Delay ( 30 pf load )
Output Enable Time ( see Fig 13 )
Output Data Delay Time ( 30 pf load )
Output Disable Time ( see Fig 13 )
Read Cycle Time
Old Data Hold Time
TPS 10
TPW 10
TPH 5
T 15
VI
TLZ 18
TDD 18
THZ 18
TRC 25
TOH 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 3. Host Controlled Output Timing. ( Advanced Data )
AUX
PDPSDSPP1166551155
DIN
O/P
S3:0
SYSTEM
CLOCK
HHOOSSTT
SYSYSSTTEEMM
Figure. 6. Host Controlled System
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