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PDF M54HC40103 Data sheet ( Hoja de datos )
| Número de pieza | M54HC40103 | |
| Descripción | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M54HC40103 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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M54/74HC40102
M54/74HC40103
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
. HIGH SPEED
fMAX = 40 MHz (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
40102B/40103B
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXXXF1R M74HCXXXXXM1R
M74HCXXXXXB1R M74HCXXXXX C1R
DESCRIPTION
The M54/74HC40102/40103 are high speed CMOS
8-STAGE PRESETTABLE SYNCHRONOUS
DOWN COUNTERS fabricated with silicon gate
C2MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while main-
taining the CMOS low power dissipation.
The HC40102, and HC40103 consist of an 8-stage
synchronous down counter with a single output
which is active when the internal count is zero. The
HC40102 is configured as two cascaded 4-bit BCD
counters, and the HC40103 contains a single 8-bit
binary counter. Each type has control inputs for en-
abling or disabling the clock, for clearing the counter
to its maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on each posi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETECT
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the J
input is clocked into the counter on the next positive
clock transition regardless of the state of the CI/CE
input.
March 1993
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
1/14
1 page  
M54/M74HC40102/40103
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
VO
Top
tr, tf
Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature: M54HC Series
M74HC Series
Input Rise and Fall Time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
Value
2 to 6
0 to VCC
0 to VCC
-55 to +125
-40 to +85
0 to 1000
0 to 500
0 to 400
Unit
V
V
V
oC
oC
ns
DC SPECIFICATIONS
Symbol
Parameter
VIH High Level Input
Voltage
VIL Low Level Input
Voltage
VOH High Level
Output Voltage
VOL Low Level Output
Voltage
II Input Leakage
Current
ICC Quiescent Supply
Current
Test Conditions
VCC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
VI =
VIH
IO=-20 µA
6.0 or
4.5 VIL IO=-4.0 mA
6.0 IO=-5.2 mA
2.0
4.5
VI =
VIH
IO= 20 µA
6.0 or
4.5 VIL IO= 4.0 mA
6.0 IO= 5.2 mA
6.0 VI = VCC or GND
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
1.5
3.15
4.2
0.5
1.35
1.8
1.9 2.0
4.4 4.5
5.9 6.0
4.18 4.31
5.68 5.8
0.0 0.1
0.0 0.1
0.0 0.1
0.17 0.26
0.18 0.26
±0.1
Value
-40 to 85 oC
74HC
Min. Max.
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
4.13
5.63
0.1
0.1
0.1
0.33
0.33
±1
-55 to 125 oC
54HC
Min. Max.
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
4.10
5.60
0.1
0.1
0.1
0.40
0.40
±1
6.0 VI = VCC or GND
4 40 80
Unit
V
V
V
V
µA
µA
5/14
5 Page 
DIM.
A
B
D
E
e3
F
G
H
L
M
N
P
Q
M54/M74HC40102/40103
Ceramic DIP16/1 MECHANICAL DATA
MIN.
0.38
2.29
0.4
1.17
0.22
0.51
7.8
mm
TYP.
3.3
17.78
MAX.
20
7
2.79
0.55
1.52
0.31
1.27
10.3
8.05
5.08
MIN.
0.015
0.090
0.016
0.046
0.009
0.020
0.307
inch
TYP.
0.130
0.700
MAX.
0.787
0.276
0.110
0.022
0.060
0.012
0.050
0.406
0.317
0.200
P053D
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet M54HC40103.PDF ] | |
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