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PDF PDSP16256B0 Data sheet ( Hoja de datos )

Número de pieza PDSP16256B0
Descripción Programmable FIR Filter
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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PDSP16256/A
Programmable FIR Filter
DS3709
Issue 7.1
June 1999
Features
q Sixteen MACs in a Single Device
q Basic Mode is 16-Tap Filter at up to 25MHz
Sample Rates
q Programmable to give up to 128 Taps with
Sampling Rates Proportionally Reducing to
3·125MHz
q 16-bit Data and 32-bit Accumulators
q Can be configured as One Long Filter or Two
Half-Length Filters
q Decimate-by-two Option will Double the Filter
Length
q Coefficients supplied from Host System or local
EPROM
Applications
q High Performance Digital Filters
Ordering Information
Commercial (0°C to 170°C)
PDSP16256A/C0/AC 25MHz, PGA package
Industrial (240°C to 185°C)
PDSP16256 B0/AC 20MHz, PGA package
PDSP16256 B0/GC 20MHz, QFP package
Military (255°C to 1125°C)
PDSP16256 MC/AC1R 20MHz, MIL-STD-883*
(latest revision), PGA package
PDSP16256 MC/GC1R 20MHz, MIL-STD-883*
(latest revision), QFP package
*See notes following Electrical Characteristics for further
information on MIL-STD-883 screening
Associated Products
PDSP16350 I/Q Splitter/NCO
PDSP16510A FFT Processor
Description
The PDSP16256 contains sixteen multiplier -
accumulators, which can be multi cycled to provide
from 16 to 128 stages of digital filtering. Input data
and coefficients are both represented by 16-bit
two’s complement numbers with coefficients
converted internally to 12 bits and the results being
accumulated up to 32 bits.
In 16-tap mode the device samples data at the
system clock rate of up to 25MHz. If a lower sample
rate is acceptable then the number of stages can be
increased in powers of two up to a maximum of 128.
Each time the number of stages is doubled, the
sample clock rate must be halved with respect to the
system clock. With 128 stages the sample clock is
therefore one eighth of the system clock.
In all speed modes devices can be cascaded to
provide filters of any length, only limited by the
possibility of accumulator overflow. The 32-bit
results are passed between cascaded devices
without any intermediate scaling and subsequent
loss of precision.
The device can be configured as either one long
filter or two separate filters with half the number of
taps in each. Both networks can have independent
inputs and outputs.
Both single and cascaded devices can be operated
in decimate-by-two mode. The output rate is then
half the input rate, but twice the number of stages
are possible at a given sample rate. A single device
with a 20MHz clock would then, for example,
provide a 128-stage low pass filter, with a 5MHz
input rate and 2·5MHz output rate.
Coefficients are stored internally and can be down
loaded from a host system or an EPROM. The latter
requires no additional support, and is used in stand
alone applications. A full set of coefficients is then
automatically loaded at power on, or at the request
of the system. A single EPROM can be used to
provide coefficients for up to 16 devices.

1 page




PDSP16256B0 pdf
PDSP16256
GG AC Signal GG AC Signal GG AC Signal GG
1 A15 F0 44 R14 SWAP 87 P1 C15 130
2 B15 F1 45
-
GND
88
-
GND
131
3
D13
F2
46 N12 OEN 89
-
GND
132
4
C14
F3
47
P13 CLKOP 90
N2
WEN
133
5
G15
VDD
48
-
VDD
91
N1
CCS
134
6 C15 F4 49 R13 DA0 92 M2 CS 135
7 D14 F5
50 P12 DA1 93
-
VDD 136
8
J15 GND 51
N11 DA2 94
L3
RES
137
9 E13 F6 52 R12 DA3 95 M1 SLCK 138
10 D15
F7
53
P11 DA4 96
M3
GND
139
11 E14
F8
54 R11 DA5 97
-
VDD 140
12 E15
F9
55
R9
GND
98
L2
BYTE
141
13 F13 F10 56 N10 DA6 99 L1 EPROM 142
14 F14 F11 57 P10 DA7 100 K3
A0 143
15 F15 F12 58 R10 DA8 101 K2
A1 144
16
-
GND
59
P9
DA9 102
K1
A2 145
17 G14 F13
60
R7
VDD 103
J2
A3 146
18 G13 F14 61
N9 DA10 104 J3
A4 147
19 H14 F15 62 P8 DA11 105 G1 VDD 148
20 - VDD 63
21 H15 F16 64
R8 DA12 106 H2
N8 DA13 107 H1
A5 149
A6 150
22 H13 F17 65
P7 DA14 108 J1
GND
151
23 J14 F18 66
R6 DA15 109 H3
A7 152
24 K15 F19 67
-
GND 110
G2
DB0 153
25 - VDD 68 N7 C0 111 F1 DB1 154
26 J13 F20 69
P6
C1 112 G3
DB2 155
27 K14 F21 70 R5 C2 113 -
GND
156
28
-
GND
71
N6 C3 114 F2 DB3 157
29 L15 F22 72 P5 C4 115 E1 DB4 158
30 K13 F23 73 R4 C5 116 F3 DB5 159
31 L14 F24 74
-
VDD 117 E2
DB6 160
32 M15 F25 75
N5
C6 118 D1
DB7 161
33 L13 F26 76 P4 C7 119 -
VDD 162
34 M14 F27 77 R3 C8 120 E3 DB8 163
35 N15 F28 78
P3
C9 121 D2
DB9 164
36
-
GND
79
N4
C10 122
C1
DB10 165
37 N14 F29 80
- GND 123 C2 DB11 166
38 M13 F30 81
R2
C11 124
D3
DB12 167
39 P15 F31 82
P2
C12 125
B1
DB13 168
40 - VDD 83
41 P14 FEN 84
N3
C13 126
B2
DB14 169
-
VDD 127
-
GND
170
42
N13 DFEN
85
- GND 128 C3 DB15 171
43 R15 DCLR 86
R1 C14 129
-
VDD 172
NOTE. All GND and VDD pins must be used
Table 2 Pin connections for AC144 and GC172 packages
AC
-
A1
A2
-
C4
B3
A3
B4
C5
A4
-
B5
A5
A7
C6
B6
A6
B7
C7
B8
A9
A8
C8
B9
A10
C9
B10
A11
C10
-
B11
A12
C11
-
B12
A13
B13
C12
A14
-
B14
-
C13
Signal
GND
BUSY
X0
VDD
X1
X2
X3
X4
X5
X6
GND
X7
X8
VDD
X9
X10
X11
X12
X13
X14
GND
X15
X16
X17
X18
X19
X20
X21
X22
GND
X23
X24
X25
VDD
X26
X27
X28
X29
X30
GND
X31
VDD
FRUN
5

5 Page





PDSP16256B0 arduino
PDSP16256
Cascading Devices
When the filter requirements are beyond the capabilities
of a single device, it is possible to connect several
devices in cascade increasing the number of taps avail-
able at the required sample rate. Within each device all
filter length, decimate, and bank swap options are still
possible, but each device in the chain must be similarly
programmed and configured as a single filter.
The number of devices which can be cascaded is only
limited by the possibility of overflow in the 32-bit interme-
diate accumulations. If more than sixteen devices are
cascaded in auto EPROM load mode, then an additional
EPROM will be needed.
In modes where the data sample rate does not equal the
clock rate. Then the cascade arrangement shown in Fig.
12 is used. Delayed data is passed from device to device
in one direction, while intermediate results flow in the
opposite direction. The interface device both accepts the
input data and produces the final result. It is not neces-
sary for each device to know its exact position in the
chain, but the device which receives the input data and
produces the final result must be identified, as must the
device which terminates the chain. The former is known
as the Interface device and the latter as the Termination
device, all others are Intermediate devices. Control
Register bits CR11:10 are used to define these positions
as shown in Table 6.
The control logic in each of the devices must be synchro-
nised with respect to the Interface device. This is achieved
by connecting the Delayed Filter Enable output (DFEN)
RESULTS
DATA IN FEN OUT
DA15:0 FEN F31:0
INTERFACE
DEVICE
DB15:0 DFEN X31:0
to the Filter Enable input (FEN) of the next device in the
chain. The Interface device, itself, needs a FEN signal
produced by the system, unless in EPROM mode, where
FRUN may be pulled high. Even when the latter is true,
the FEN connection must be made between the remain-
ing devices in the chain. By effectively extending the
filter length, the cascade latency is therefore the same
as for the single device in the same mode. Once the
pipeline is initially flushed the latency is as given in
Table 3.
When devices are cascaded such that the data sample
rate equals the clock rate, (Control register bits 14:13 =
00), then a different cascade configuration must be
used. This is shown in Fig. 13. The number of devices
that can be cascaded is, again, only limited by the 32-bit
accumulators.
In this mode the delayed data is passed from device to
device in the same direction as the intermediate results.
The device which accepts the input data is now at the
opposite end of the chain to the device which produces
the final result. The control logic in each of the devices
must be synchronised this is achieved by connecting all
the device FEN inputs to the global FEN. The cascade
latency for the complete filter is built up from the 12
delays from the termination device, 8 delays from the
interface device and additional intermediate devices
each adding 4 delays.
Avalable Options
No more than 128 coefficients can be stored internally.
This limits the filter length / decimate / bank swap options
to those which do not require more than that number of
coefficients. Thus when a filter with 128 taps is to be
implemented in a single device, it is not possible to
decimate or bank swap. When a filter with 64 taps is
implemented, decimate or bank swap are possible, but
not both. With all other filter lengths, all decimate and
bank swap configurations are possible.
DA15:0 FEN F31:0
INTERMEDIATE
DEVICE
DB15:0 DFEN X31:0
DA15:0 FEN F31:0
TERMINATION
DEVICE
DB15:0 DFEN X31:0
Figure. 12 Three-device cascaded system
11

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