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PDF M54HC113F1R Data sheet ( Hoja de datos )

Número de pieza M54HC113F1R
Descripción DUAL J-K FLIP FLOP WITH PRESET
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M54HC113
M74HC113
DUAL J-K FLIP FLOP WITH PRESET
. HIGH SPEED
fMAX = 71 MHz (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA at TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS113
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 11 3F 1R
M 74H C1 13 M1 R
M 74HC 11 3B 1R
M 74H C1 13 C1 R
The M54/74HC113 is a high speed CMOS DUAL J-
K FLIP FLOP WITH PRESET fabricated in silicon
gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption. This circuit offers in-
dividual J, K, set, and clock inputs. These monolithic
dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH
and the bistable will function as shown in the truth
table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on
the negative-going edge of the clock pulse. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
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1 page




M54HC113F1R pdf
M54/M74HC113
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(CK - Q, Q)
2.0
4.5
6.0
46 125 155 190
16 25 31 38 ns
12 21 26 32
tPLH Propagation
2.0
tPHL Delay Time
4.5
(PRESET - Q, Q) 6.0
48 125 155 190
16 25 31 38 ns
13 21 26 32
fMAX Maximum Clock 2.0
Frequency
4.5
8 16
40 63
6.4 5.4
32 27 MHz
6.0 47 79 38 32
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
2.0
4.5
6.0
16 75
4 15
3 13
95 110
19 22 ns
16 19
tW(L) Minimum Pulse
Width
(PRESET)
2.0
4.5
6.0
16 75
4 15
3 13
95 110
19 22 ns
16 19
ts Minimum Set-up 2.0
Time
4.5
16 50 65 75
4 10 13 15 ns
6.0
39
11 13
th Minimum Hold 2.0
Time
4.5
000
0 0 0 ns
6.0 0 0 0
tREM Minimum
Removal Time
(PRESET)
2.0
4.5
6.0
555
5 5 5 ns
555
CIN Input Capacitance
5 10
10 1 0 pF
CPD (*) Power Dissipation
Capacitance
37
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/2 (per FLIP/FLOP)
5/11

5 Page





M54HC113F1R arduino
M54/M74HC113
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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