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PDF PDSP16116DB0GG Data sheet ( Hoja de datos )

Número de pieza PDSP16116DB0GG
Descripción 16 X 16 Bit Complex Multiplier
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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Supersedes October 1996 version, DS3707 - 4.2
PDSP16116
16 X 16 Bit Complex Multiplier
DS3707 - 5.3 October 1997
The PDSP16116 contains four 16316 array multipliers, two
32-bit adder/subtractors and all the control logic required to sup-
port Block Floating Point Arithmetic as used in FFT applications.
The PDSP16116A variant will multiply two complex (16116)
bit words every 50ns and can be configured to output the com-
plete complex (32132) bit result within a single cycle. The data
format is fractional two’s complement.
In combination with a PDSP16318A, the PDSP16116A forms
a two-chip 20MHz complex multiplier accumulator with 20-bit
accumulator registers and output shifters. The PDSP16116A in
combination with two PDSP16318As and two PDSP1601As
forms a complete 20MHz Radix 2 DIT FFT butterfly solution
which fully supports block floating point arithmetic. The
PDSP16116 has an extremely high throughput that is suited to
recursive algorithms as all calculations are performed with a
single pipeline delay (two cycle fall-through).
FEATURES
I Complex Number (16116)3(16116) Multiplication
I Full 32-bit Result
I 20MHz Clock Rate
I Block Floating Point FFT Butterfly Support
I (21)3(21) Trap
I Two’s Complement Fractional Arithmetic
I TTL Compatible I/O
I Complex Conjugation
I 2 Cycle Fall Through
I 144-pin PGA or QFP packages
APPLICATIONS
I Fast Fourier Transforms
I Digital Filtering
I Radar and Sonar Processing
I Instrumentation
I Image Processing
ORDERING INFORMATION
PDSP16116 MC GGDR 10MHz MIL-883 screened
PDSP16116A B0 AC 20MHz Industrial
PDSP16116A A0 AC 20MHz Military
PDSP16116A B0 GG 20MHz Industrial
PDSP16116A MC GGDR 20MHz MIL-883 screened
PDSP16116B B0 AC 25MHz Industrial
PDSP16116D B0 GG 31·5MHz Industrial
XR15:0
XI15:0
YR15:0
YI15:0
REG REG REG REG
MULT
MULT
MULT
MULT
REG REG REG REG
ADD/SUB
ADD/SUB
SHIFT
SHIFT
REG REG
PR15:0
PI15:0
Fig. 1 Simplified block diagram
ASSOCIATED PRODUCTS
PDSP16318/A Complex Accumulator
PDSP16112/A (16116)3(12112) Complex Multiplier
PDSP16330/A Pythagoras Processor
PDSP1601/A ALU and Barrel Shifter
PDSP16350 Precision Digital Modulator
PDSP16256 Programmable FIR Filter
PDSP16510 Single Chip FFT Processor

1 page




PDSP16116DB0GG pdf
PDSP16116
GG AC Signal GG AC Signal GG AC Signal GG
1
D3 PI14 37
N4
XI1 73
P2
GND
109
2
C2 PI15 38
P3
XI2 74 R1 VDD 110
3
B1 WTOUT1 39
R2
XI3 75
P15 YR12 111
4
D2 WTOUT0 40
P4
XI4 76
M14 YR11 112
5
E3 SFTR0 41
N5
XI5 77
L13 YR10 113
6 C1 SFTR1 42 R3 XI6 78 N15 YR9 114
7 E2 SFTR2 43 P5 XI7 79 L14 YR8 115
8 D1 OEI 44 R4 XI8 80 M15 YR7 116
9 F2 CONY 45 N6 XI9 81 K13 YR6 117
10 F3 CONX 46 P6 XI10 82 K14 YR5 118
11 E1 ROUND 47 R5 XI11 83 L15 YR4 119
12 G2 AI13 48 P7 XI12 84 J14 YR3 120
13 G3 AI14 49 N7 XI13 85 J13 YR2 121
14 F1 AI15 50 R6 XI14 86 K15 YR1 122
15 G1 AR13 51 R7 XI15 87 J15 YR0 123
16
H2 AR14 52
P8
CEY 88
H14 EOPSS 124
17 H1 AR15 53 R8 CEX 89 H15 VDD 125
18
H3
YI15
54
N8 XR15 90 H13 SOBFP 126
19
J3
YI14
55
N9 XR14 91 G13 WTB1 127
20
J1
YI13
56
R9 XR13 92 G15 WTB0 128
21 K1 YI12 57 R10 XR12 93 F15 WTA1 129
22 J2 YI11 58 P9 XR11 94 G14 WTA0 130
23 K2 YI10 59 P10 XR10 95 F14 MBFP 131
24 K3 YI9 60 N10 XR9 96 F13 CLK 132
25 L1 YI8 61 R11 XR8 97 E15 OSEL1 133
26 L2 YI7 62 P11 XR7 98 E14 OSEL0 134
27 M1 YI6 63 R12 XR6 99 D15 OER 135
28
N1
YI5
64
R13
XR5 100
C15 SFTA0 136
29
M2
YI4
65
P12
XR4 101
D14 SFTA1 137
30
L3
YI3
66
N11
XR3 102
E13 GWR0 138
31
N2
YI2
67
P13
XR2 103
C14 GWR1 139
32
P1
YI1
68
R14
XR1 104
B15 GWR2 140
33
M3
YI0
69
N12
XR0 105
D13 GWR3 141
34 N3 XI0 70 N13 YR15 106 C13 GWR4 142
35
B2
GND
71
P14 YR14 107
B14
PR15
143
36
A1
VDD
72
R15 YR13 108
A15
PR14
144
NOTE. All GND and VDD pins must be used
Table 2 Pin connections for AC144 (Power) and GG144 packages
AC
N14
M13
A14
B12
C11
A13
B11
A12
C10
B10
A11
B13
C12
A10
A9
B8
A8
C8
C7
A7
A6
B7
B6
C6
A5
B5
A4
A3
B4
C5
B3
A2
C4
C3
B9
C9
Signal
VDD
GND
PR13
PR12
PR11
PR10
PR9
PR8
PR7
PR6
PR5
GND
VDD
PR4
PR3
PR2
PR1
PR0
PI0
PI1
PI2
PI3
PI4
VDD
PI5
GND
PI6
PI7
PI8
PI9
PI10
PI11
PI12
PI13
GND
VDD
5

5 Page





PDSP16116DB0GG arduino
PDSP16116
CLK
SOBFP
EOPSS
A, B, W,
WTA, WTB
A, B, BTOUT
GWR
1234567
n21 n
12 3
n25 n24 n23 n22 n21 n
123
START OF
FIRST PASS
NOTES
1. 1 = FIRST CYCLE OF DATA IN PASS
2. n = LAST CYCLE OF DATA IN PASS
Fig. 7 Use of the BFP control signals
END OF FIRST PASS/
START OF NEXT PASS
(MINIMUM NUMBER OF
LAY CYCLES SHOWN).
PERIOD BETWEEN
OTHER INTERMEDIATE
PASSES IS SIMILAR.
In practice, data output may never approach the theoretical
maximum. Hence, it may be worthwhile to try various universal
exponents and choose the one best suited to the particular ap-
plication.
Data is output from the butterfly processor with a two-part
exponent: the 5-bit GWR applicable to all data words from a
given FFT and a 2-bit WTOUT associated with each individual
dataword. To find the complete exponent for a given word, the
GWR for that FFT must be modified by its WTOUT as shown in
Table 6. The result is the number of places the binary point has
shifted to the right during the course of the FFT.
This value must be compared with the universal exponent to
determine the shift required. This is done by subtracting it from
the universal exponent. The number of places to be shifted is
equal to the difference between the two exponents. The shift
can be implemented in a PDSP1601/A (the shift value is fed
into the SV port).
As FFT data consists of real and imaginary parts, either two
PDSP1601/As must be used (controlled by the same logic) or a
single PDSP1601/A could be used handling real and imaginary
data on alternate cycles (using the same instructions for both
cycles).
An example of an output normalisation circuit is shown
in Fig.8. Only 4-bit data paths are used in calculating the
shift. This means that we must be able to trap very small
values negative of GWR and force a 15-bit right shift in
such cases.
NB It is easier to simply add the word tag to the exponent for the
purpose of determing the shift required, instead of modifying it
according to Table.6. To compensate for this, the universal ex-
ponent may be increased by one.
WTOUT GWR
UNIVERSAL 4-BIT ADDER
EXPONENT
16-BIT DATA
SIGN
BIT
4-BIT SUBTRACTOR
1111
4-BIT MUX
SV PORT
B PORT
PDSP1601
C PORT
ASRSV
NORMALISED OUTPUT DATA
Fig. 8 Output normalisation circuit
11

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