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PDF PDSP1601MCGGCR Data sheet ( Hoja de datos )
| Número de pieza | PDSP1601MCGGCR | |
| Descripción | ALU and Barrel Shifter | |
| Fabricantes | Mitel Networks Corporation | |
| Logotipo |  |
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PDSP160P1D/SPPD160S1/PPD1S6P016101AA
ALU and Barrel Shifter
Supersedes version DS3705 - 2.3 September 1996
DS3705 - 3.0 November 1998
The PDSP1601 is a high performance 16-bit arithmetic
logic unit with an independent on-chip 16-bit barrel shifter.
The PDSP1601A has two operating modes giving 20MHz or
10MHz register-to-register transfer rates.
The PDSP1601 supports Multicycle multiprecision
operation. This allows a single device to operate at 20MHz for
16-bit fields, 10MHz for 32-bit fields and 5MHz for 64-bit fields.
The PDSP1601 can also be cascaded to produce wider words
at the 20MHz rate using the Carry Out and Carry In pins. The
Barrel Shifter is also capable of extension, for example the
PDSP1601 can used to select a 16-bit field from a 32-bit input
in 100ns.
PIN 1A INDEX MARK
ON TOP SURFACE
A
B
C
D
E
F
G
H
J
K
L
11 10 9 8 7 6 5 4 3 2 1
AC84
FEATURES
s 16-bit, 32 instruction 20MHz ALU
s 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter
s Independent ALU and Shifter Operation
s 4 x 16-bit On Chip Scratchpad Registers
s Multiprecision Operation; e.g. 200ns 64-bit
Accumulate
s Three Port Structure with Three Internal Feedback
Paths Eliminates I/O Bottlenecks
s Block Floating Point Support
s 300mW Maximum Power Dissipation
s 84-pin Pin Grid Array or 84 Contact LCC Packages
or 100 pin Ceramic Quad Flat Pack
APPLICATIONS
s Digital Signal Processing
s Array Processing
s Graphics
s Database Addressing
s High Speed Arithmetic Processors
ASSOCIATED PRODUCTS
PDSP16112 Complex Multiplier
PDSP16116 16 x 16 Complex Multiplier
PDSP16318 Complex Accumulator
PDSP16330 Pythagoras Processor
GC100
Fig.1 Pin connections - bottom view
ORDERING INFORMATION
PDSP1601 MC GGCR 10MHz MIL883 Screened -
QFP package
PDSP1601A BO AC
20MHz Industrial - PGA
package
N.B Further details of the Military grade part are
available in a separate datasheet (DS3763)
1
1 page  
PDSP1601/PDSP1601A
Table 1 ALU instructions
1a. ARITHMETIC INSTRUCTIONS
Inst IA4-AI0 Mnemonic Operation
Function
00 00000 CLRXX RESET
01 00001 MIAX1 MINUS A
02 00010 MIACI MINUS A
03 00011 MIACO MINUS A
04 00100 A2SGN A/2
05 00101 A2RAL A/2
06 00110 A2RAR A/2
07 00111 A2RSX A/2
08 01000 APBCI A PLUS B
09 01001 APBCO A PLUS B
0A 01010 AMBX1 A MINUS B
0B 01011 AMBCI A MINUS B
0C 01100 AMBCO A MINUS B
0D 01101 BMAX1 B MINUS A
0E 01110 BMACI B MINUS A
0F 01111 BMACO B MINUS A
CLEAR ALL REGISTERS
NA Plus 1
NA Plus CI
NA Plus CO
A/2 Sign Extend
A/2 with RAL LSB
A/2 with RAR LSB
A/2 with RSX LSB
A Plus B Plus CI
A Plus B Plus CO
A Plus NB Plus 1
A Plus NB Plus CI
A Plus NB Plus CO
NA Plus B Plus 1
NA Plus B Plus CI
NA Plus B Plus CO
Mode
---------
LSBYTE
CASCADE
MULTICYCLE
MSBYTE
MULTICYCLE
MULTICYCLE
MULTICYCLE
CASCADE
MULTICYCLE
LSBYTE
CASCADE
MULTICYCLE
LSBYTE
CASCADE
MULTICYCLE
1b. LOGICAL INSTRUCTIONS
Inst IA4-AI0 Mnemonic Operation Function
10 10000 ANXAB A AND B
11 10001 ANANB A AND NB
12 10010 ANNAB NA AND B
13 10011 ORXAB A OR B
14 10100 ORNAB NA OR B
15 10101 XORAB A XOR B
16 10110 PASXA PASS A
17 10111 PASNA INVERT A
A. B
A. NB
NA. B
A+B
NA + B
A XOR B
A
NA
1c. CONTROL INSTRUCTIONS
Inst IA4-AI0 Mnemonic
Operation
18 11000 SBFOV Set BFP Flag to OVR, Force ALU output to zero
19 11001 SBFU1 Set BFP Flag to UND 1 Force ALU output to zero
1A 11010 SBFU2 Set BFP Flag to UND 2 Force ALU output to zero
1B 11011 SBFZE Set BFP Flag to ZERO Force ALU output to zero
1C 11100 OPONE Output 0001 Hex
1D 11101 OPBYT Output 00FF Hex
1E 11110 OPNIB Output 000F Hex
1F 11111 OPALT Output 5555 Hex
KEY
A
B
CI
CO
RAL
RAR
RSX
= A input to ALU
= B input to ALU
= External Carry in to ALU
= Internally Registered Carry out from ALU
= ALU Register (Left)
= ALU Register (Right)
= Shifter Register (Left or Right)
MNEMONICS
CLRXX Clear All Registers to zero
MIAXX Minus A,
XX = Carry in to LSB
A2XXX A Divided by 2, XXX = Source of MSB
APBXX A Plus B,
XX = Carry in to LSB
AMBXX A Minus B,
XX = Carry in to LSB
BMAXX B Minus A,
XX = Carry in to LSB
ANX-Y AND
X = Operand 1, Y = Operand 2
ORX-Y OR
X = Operand 1, Y = Operand 2
XORXY Exclusive OR X = Operand 1, Y = Operand 2
PASXX Pass
XX = Operand
SBFXX Set BFP Flag XX = Function
OPXXX Output Constant XXX
5
5 Page 
PDSP1601/PDSP1601A
ALU Control Instructions
Mnemonic Op Code
SBFOV
<18>
SBFU1
<19>
SBFU2
<1A>
SBFZE
OPONE
OPBYT
OPNIB
OPALT
<1B>
<1C>
<1D>
<1E>
<1F>
Function
The BFP flag is programmed to activate when an ALU operation causes an overflow of the
16 bit number range. This flag is logically the exclusive-or of the carry into and out of the
MSB of the ALU. For the most significant Byte this flag indicates that the result of an
arithmetic two's complement operation has overflowed into the sign bit. The output of the
ALU is forced to zero for the duration of this instruction.
The BFP flag is programmed to activate when an ALU operation comes within a factor of
two of causing an overflow of the 16 bit number range. For the most significant Byte this
flag indicates that the result of an arithmetic two's complement operation is within a factor
of two of overflowing into the sign bit. The output of the ALU is forced to zero for the duration
of this instruction.
The BFP flag is programmed to activate when an ALU operation comes within a factor of
four of causing an overflow of the 16 bit number range. For the most significant Byte this
flag indicates that the result of an arithmetic two's complement operation is within a factor
of four of overflowing into the sign bit. The output of the ALU is forced to zero for the duration
of this instruction.
The BFP flag is programmed to activate when an ALU operation causes a result of zero.
The output of the ALU is forced to zero for the duration of this instruction. During the
execution of this instruction the BFP flag will become active.
The ALU will output the binary value 0000000000000001, the MSB on the left.
The ALU will output the binary value 0000000011111111, the MSB on the left.
The ALU will output the binary value 0000000000001111, the MSB on the left.
The ALU will output the binary value 0101010101010101, the MSB on the left.
Barrel Shifter Instructions
Mnemonic Op Code
Function
LSRSV
<0> The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the SV register. The LSBs are dicarded,
and the vacant MSBs are filled with zeros.
LSLSV
<1> The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number present in the SV register. The LSBs are dicarded, and
the vacant MSBs are filled with zeros.
BSRSV
<2> The 16 bit input to the Barrel Shifter is rotated to the right by the number of places indicated
by the magnitude of the four bit number present in the SV register. The LSBs that exit the
16 bit field to the right, reappear in the vacant MSBs on the left.
BSLSV
<3> The 16 bit input to the Barrel Shifter is rotated to the left by the number of places indicated
by the magnitude of the four bit number present in the SV register. The LSBs that exit the
16 bit field to the right, reappear in the vacant MSBs on the right.
LSRR1
<4> The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number resident within the R1 register. The LSBs are
discarded, and the vacant MSBs are filled with zeros.
LSLR1
<5> The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number resident within the R1 register. The LSBs are discarded,
and the vacant LSBs are filled with zeros.
LSRR2
<6> The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number resident within the R2 register. The LSBs are
discarded, and the vacant MSBs are filled with zeros.
LSLR2
<7> The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number resident within the R2 register. The LSBs are discarded,
and the vacant LSBs are filled with zeros.
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet PDSP1601MCGGCR.PDF ] | |
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