PDF M50LPW040 Data sheet ( Hoja de datos )

Número de pieza	M50LPW040
Descripción	4 Mbit 512Kb x8/ Uniform Block 3V Supply Low Pin Count Flash Memory
Fabricantes	ST Microelectronics
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M50LPW040 4 Mbit (512Kb x8, Uniform Block) 3V Supply Low Pin Count Flash Memory PRELIMINARY DATA s SUPPLY VOLTAGE – VCC = 3V to 3.6V for Program, Erase and Read Operations – VPP = 12V for Fast Program and Fast Erase (optional) s TWO INTERFACES – Low Pin Count (LPC) Standard Interface for embedded operation with PC Chipsets. – Address/Address Multiplexed (A/A Mux) In- terface for programming equipment compati- bility. s LPC HARDWARE INTERFACE MODE – 5 Signal Communication Interface supporting Read and Write Operations – Hardware Write Protect Pins for Block Pro- tection – Register Based Read and Write Protection – 5 Additional General Purpose Inputs for plat- form design flexibility – Synchronized with 33 MHz PCI clock s PROGRAMMING TIME – 10µs typical – Quadruple Byte Programming Option s 8 UNIFORM 64 Kbyte MEMORY BLOCKS s PROGRAM/ERASE CONTROLLER – Embedded Byte Program and Block/Chip Erase algorithms – Status Register Bits s PROGRAM and ERASE SUSPEND – Read other Blocks during Program/Erase Suspend – Program other Blocks during Erase Suspend s FOR USE in PC BIOS APPLICATIONS s ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 26h TSOP40 (N) 10 x 20mm PLCC32 (K) Figure 1. Logic Diagram (LPC Interface) VCC VPP 3 ID0-ID2 GPI0- GPI4 5 4 LAD0- LAD3 WP LFRAME CLK IC RP INIT M50LPW040 TBL VSS AI05435 March 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/36 1 page M50LPW040 Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 7) from being changed. When Top Block Lock, TBL, is set Low, VIL, Program and Block Erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to 6). Top Block Lock, TBL, must be set prior to a Pro- gram or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL during Program or Erase Suspend. Write Protect (WP). The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being changed. When Write Protect, WP, is set Low, VIL, Program and Block Erase operations in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 7). Write Protect, WP, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or un- predictable results may occur. Care should be tak- en to avoid unpredictable behavior by changing WP during Program or Erase Suspend. Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They must be left disconnected. (Pin 9 in the PLCC32, and Pin 21 in the TSOP40, may also be driven High or driven Low.) Address/Address Multiplexed (A/A Mux) Signal Descriptions For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logic Diagram, and Table 3, Signal Names. Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A18). They are latched during any bus operation by the Row/Col- umn Address Select input, RC. Data Inputs/Outputs (DQ0-DQ7). The Data In- puts/Outputs hold the data that is written to or read Table 3. Signal Names (A/A Mux Interface) IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G Output Enable W Write Enable RC Row/Column Address Select RB Ready/Busy Output RP Interface Reset VCC Supply Voltage Optional Supply Voltage for Fast VPP Program and Fast Erase Operations VSS Ground NC Not Connected Internally from the memory. They output the data stored at the selected address during a Bus Read opera- tion. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. The Data Inputs/Out- puts, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on the rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or Erase operation. 5/36 5 Page M50LPW040 Read Memory Array Command. The Read Mem- ory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is is- sued the memory remains in Read mode until an- other command is issued. From Read mode Bus Read operations will access the memory array. While the Program/Erase Controller is executing a Program or Erase operation the memory will not accept the Read Memory Array command until the operation completes. Read Status Register Command. The Read Sta- tus Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read opera- tions read the Status Register until another com- mand is issued. See the section on the Status Register for details on the definitions of the Status Register bits. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until a Read Memory Array command is issued. After the Read Electronic Signature Command is issued the Manufacturer Code and Device Code can be read using Bus Read operations using the addresses in Table 10. Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the address falls in a protected block then the Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 12. Note that the Program command cannot change a bit set at ‘0’ back to ‘1’ and attempting to do so will Table 10. Read Electronic Signature Code Address Manufacturer Code 00000h Device Code 00001h Note: For A19 value, refer to Table 2. Data 20h 26h not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 14, Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command. Quadruple Byte Program Command. The Qua- druple Byte Program Command can be only used in A/A Mux mode to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. The operation can also be executed if VPP is below VPPH, but result could be uncertain. Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend com- mand. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table 12. Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 15, Quadruple Byte Program Flow- chart and Pseudo Code, for a suggested flowchart on using the Quadruple Byte Program command. Chip Erase Command. The Chip Erase Com- mand can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be at- tempted when VPP is not at VPPH. The operation can also be executed if VPP is below VPPH, but re- sult could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the 11/36 11 Page

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