PDF M50LPW012 Data sheet ( Hoja de datos )

Número de pieza	M50LPW012
Descripción	2 Mbit 256Kb x8/ Boot Block 3V Supply Low Pin Count Flash Memory
Fabricantes	ST Microelectronics
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M50LPW012 2 Mbit (256Kb x8, Boot Block) 3V Supply Low Pin Count Flash Memory PRELIMINARY DATA s SUPPLY VOLTAGE – VCC = 3V to 3.6V for Program, Erase and Read Operations – VPP = 12V for Fast Program and Fast Erase s LOW PIN COUNT (LPC) – Standard Interface for embedded operation with PC Chipsets that are without automap- ping memory features s ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) – Interface for programming equipment com- patibility s LOW PIN COUNT (LPC) HARDWARE INTERFACE MODE – 5 Signal Communication Interface supporting Read and Write Operations – Hardware Write Protect Pins for Block Pro- tection – Register Based Read and Write Protection – 5 Additional General Purpose Inputs for plat- form design flexibility – Synchronized with 33MHz PCI clock s BYTE PROGRAMMING TIME – Single Byte Mode 10µs typical – Quadruple Byte Mode 2.5µs typical s 7 MEMORY BLOCKS – 1 Boot Block – 4 Main Blocks and 2 Parameter Blocks s PROGRAM/ERASE CONTROLLER – Embedded Byte Program and Block/Chip Erase algorithms – Status Register Bits s PROGRAM and ERASE SUSPEND s FOR USE in PC BIOS APPLICATIONS s ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 3Bh PLCC32 (K) Figure 1. Logic Diagram (LPC Interface) VCC VPP 4 ID0-ID3 GPI0- GPI4 5 4 LAD0- LAD3 WP LFRAME CLK IC RP INIT M50LPW012 TBL VSS AI06949 September 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/35 1 page M50LPW012 be changed until the operation completes or un- predictable results may occur. Care should be tak- en to avoid unpredictable behavior by changing WP during Program or Erase Suspend. Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They may be left disconnected or driven Low, VIL, or High, VIH. Address/Address Multiplexed (A/A Mux) Signal Descriptions For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logic Diagram, and Table 4, Signal Names. Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A17). They are latched during any bus operation by the Row/Col- umn Address Select input, RC. Data Inputs/Outputs (DQ0-DQ7). The Data In- puts/Outputs hold the data that is written to or read from the memory. They output the data stored at the selected address during a Bus Read opera- tion. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. The Data Inputs/Out- puts, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A17). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on the rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or Erase operation. Supply Signal Descriptions The Supply Signals are the same for both interfac- es. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, Table 4. Signal Names (A/A Mux Interface) IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G Output Enable W Write Enable RC Row/Column Address Select RB Ready/Busy Output RP Interface Reset VCC Supply Voltage Optional Supply Voltage for Fast VPP Program and Fast Erase Operations VSS Ground NC Not Connected Internally VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After VCC becomes valid the Command Interface is reset to Read mode. A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both VCC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory. VPP can be left floating. When VPP = VPPH Fast Program (if a Quadruple Byte Program Command is performed) and Fast Erase operations are used. VPP should not be set to VPPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the volt- age measurements. 5/35 5 Page M50LPW012 Quadruple Byte Program Command. The Qua- druple Byte Program Command can be only used in A/A Mux mode to program four adjacent Bytes in the memory array at a time. The four Bytes must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. The operation can also be executed if VPP is below VPPH, but result could be uncertain. Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third Byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth Byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend com- mand. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table 13. Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 14, Quadruple Byte Program Flow- chart and Pseudo Code, for a suggested flowchart on using the Quadruple Byte Program command. Chip Erase Command. The Chip Erase Com- mand can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be at- tempted when VPP is not at VPPH. The operation can also be executed if VPP is below VPPH, but re- sult could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Chip Erase operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Chip Erase times are given in Table 13. The Chip Erase command sets all of the bits in the memory to ‘1’. See Figure 16, Chip Erase Flow- chart and Pseudo Code, for a suggested flowchart on using the Chip Erase command. Block Erase Command. The Block Erase com- mand can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Pro- Table 11. Read Electronic Signature Code Address Manufacturer Code 00000h Device Code 00001h Note: For A19:18 values, see Table 2. Data 20h 3Bh gram/Erase Controller. Once the command is is- sued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the block is protected then the Block Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. During the Block Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Block Erase times are given in Table 13. The Block Erase command sets all of the bits in the block to ‘1’. All previous data in the block is lost. See Figure 17, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Clear Status Register Command. The Clear Sta- tus Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the mem- ory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Sta- tus Register by issuing the Clear Status Register command before attempting a new Program or Erase command. Program/Erase Suspend Command. The Pro- gram/Erase Suspend command can be used to pause a Program or Block Erase operation. One Bus Write cycle is required to issue the Program/ Erase Suspend command and pause the Pro- gram/Erase Controller. Once the command is is- sued it is necessary to poll the Program/Erase Controller Status bit to find out when the Program/ Erase Controller has paused; no other commands will be accepted until the Program/Erase Control- ler has paused. After the Program/Erase Control- ler has paused, the memory will continue to output the Status Register until another command is is- sued. 11/35 11 Page

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