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PDF M50LPW002 Data sheet ( Hoja de datos )
| Número de pieza | M50LPW002 | |
| Descripción | 2 Mbit 256Kb x8/ Boot Block 3V Supply Low Pin Count Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M50LPW002
2 Mbit (256Kb x8, Boot Block)
3V Supply Low Pin Count Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VCC = 3 V to 3.6 V for Program, Erase and
Read Operations
– VPP = 12 V for Fast Program and Fast Erase
(optional)
s TWO INTERFACES
– Low Pin Count (LPC) Standard Interface for
embedded operation with PC Chipsets.
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility.
s LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33 MHz PCI clock
s PROGRAMMING TIME
– 10 µs typical
– Quadruple Byte Programming Option
s 7 MEMORY BLOCKS
– 1 Boot Block (Top Location)
– 4 Main Blocks and 2 Parameter Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte Program, Block Erase and
Chip Erase algorithms
– Status Register Bits
s PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase Suspend
s FOR USE in PC BIOS APPLICATIONS
Figure 1. Packages
PLCC32 (K)
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 31h
May 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/39
1 page  
Figure 3. Logic Diagram (LPC Interface)
VCC VPP
4
ID0-ID3
GPI0-
GPI4
5
4
LAD0-
LAD3
WP
LFRAME
CLK
IC
RP
INIT
M50LPW002
TBL
VSS
AI05742
Table 1. Signal Names (LPC Interface)
LAD0-LAD3 Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID3
Identification Inputs
GPI0-GPI4 General Purpose Inputs
IC Interface Configuration
RP Interface Reset
INIT CPU Reset
CLK
Clock
TBL Top Block Lock
WP Write Protect
RFU
Reserved for Future Use. Leave
disconnected
VCC Supply Voltage
VPP
Optional Supply Voltage for Fast
Erase Operations
VSS Ground
NC Not Connected Internally
M50LPW002
Figure 4. Logic Diagram (A/A Mux Interface)
VCC VPP
11
A0-A10
8
DQ0-DQ7
RC
M50LPW002
IC RB
G
W
RP
VSS
AI05743
Table 2. Signal Names (A/A Mux Interface)
IC Interface Configuration
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
G Output Enable
W Write Enable
RC Row/Column Address Select
RB Ready/Busy Output
RP Interface Reset
VCC Supply Voltage
VPP
Optional Supply Voltage for Fast
Program and Fast Erase Operations
VSS Ground
NC Not Connected Internally
5/39
5 Page 
M50LPW002
Table 6. Bus Write Field Definitions (LPC Interface)
Clock Clock
Cycle Cycle
Number Count
Field
LAD0-
LAD3
Memory
I/O
Description
On the rising edge of CLK with LFRAME Low, the contents
1 1 START 0000b I of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
CYCTY
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
2
1
PE +
011Xb
I indicates the direction of transfer: 1b for write. Bit 0 is don’t
DIR care (X).
3-10
8
ADDR
XXXX
A 32-bit address phase is transferred starting with the most
I
significant nibble first. A23-A31 must be set to 1. A22 = 1 for
Array, A22 = 0 for registers access. For A18-A21 values,
refer to Table 3.
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the least significant
nibble.
13 1 TAR 1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating it has received data or a command.
16
1 TAR 1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b,
indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and the host takes
control of LAD0-LAD3.
Figure 6. Bus Write Waveforms (LPC Interface)
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
1
CYCTYPE
+ DIR
1
ADDR
8
DATA
2
TAR
2
SYNC
1
TAR
2
AI04430
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