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PDF M4T28-BR12SH Data sheet ( Hoja de datos )

Número de pieza M4T28-BR12SH
Descripción TIMEKEEPER SNAPHAT Battery & Crystal
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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M41ST85Y
M41ST85W
5.0 OR 3.0V, 512 bit (64 x 8) SERIAL
RTC and NVRAM SUPERVISOR
FEATURES SUMMARY
s 5.0 OR 3.0V OPERATING VOLTAGE
s SERIAL INTERFACE SUPPORTS I2C BUS
(400 KHz)
s NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
s OPTIMIZED FOR MINIMAL INTERCONNECT
TO MCU
s 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
s AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
s CHOICE OF POWER-FAIL DESELECT
VOLTAGES
– M41ST85Y: VCC = 4.5 to 5.5V;
4.20V VPFD 4.50V
– M41ST85W: VCC = 2.7 to 3.6V;
2.55V VPFD 2.70V
s 1.25V REFERENCE (for PFI/PFO)
s COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
s 44 BYTES OF GENERAL PURPOSE RAM
s PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
s WATCHDOG TIMER
s MICROPROCESSOR POWER-ON RESET
s BATTERY LOW FLAG
s POWER-DOWN TIMESTAMP (HT BIT)
s ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (MAX)
s PACKAGING INCLUDES A 28-LEAD SOIC and
SNAPHAT® TOP (to be Ordered Separately)
s SOIC SNAPHAT PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY and
CRYSTAL
s SOIC EMBEDDED CRYSTAL PACKAGE (MX)
OPTION
Figure 1. 28-pin SOIC Package
SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
Figure 2. 28-pin (300mil) SOIC Package
EMBEDDED Crystal
SOX28 (MX)
May 2003
Rev. 4.0
1/33

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M4T28-BR12SH pdf
Figure 3. Logic Diagram
VCC VBAT(1)
SCL
SDA
EX
RSTIN1
RSTIN2
WDI
PFI
M41ST85Y
M41ST85W
ECON
RST
IRQ/FT/OUT
SQW
PFO
VOUT
VSS
AI03658
Note: 1. For 28-pin, 300mil embedded crystal SOIC only.
M41ST85Y, M41ST85W
Table 1. Signal Names
ECON
Conditioned Chip Enable Output
EX External Chip Enable
IRQ/FT/OUT
Interrupt/Frequency Test/Out Output
(Open Drain)
PFI Power Fail Input
PFO
Power Fail Output
RST
Reset Output (Open Drain)
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
SCL
Serial Clock Input
SDA
Serial Data Input/Output
SQW
Square Wave Output
WDI
Watchdog Input
VCC Supply Voltage
VOUT
Voltage Output
VSS Ground
VBAT(1)
Battery Supply Voltage
Note: 1. For 28-pin, 300mil embedded crystal SOIC only.
Figure 4. 28-pin SOIC Connections
SQW
NC
NC
NC
NC
NC
NC
WDI
RSTIN1
RSTIN2
NC
NC
PFO
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 M41ST85Y 22
8 M41ST85W 21
9 20
10 19
11 18
12 17
13 16
14 15
AI03659
VCC
EX
IRQ/FT/OUT
VOUT
NC
NC
PFI
NC
SCL
NC
RST
NC
SDA
ECON
Figure 5. 28-pin, 300mil SOIC (MX)
Connections
NC
NC
NC
NC
NC
NC
NC
SQW
WDI
RSTIN1
RSTIN2
PFO
NC
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 M41ST85Y 22
8 M41ST85W 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
EX
IRQ/FT/OUT
VOUT
VSS
PFI
SCL
NC
NC
RST
NC
SDA
ECON
VBAT
AI06370c
5/33

5 Page





M4T28-BR12SH arduino
M41ST85Y, M41ST85W
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Figure 9. Serial Bus Data Transfer Sequence
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
Figure 10. Acknowledgement Sequence
SCL FROM
MASTER
START
1
DATA OUTPUT
BY TRANSMITTER
MSB
DATA OUTPUT
BY RECEIVER
2
STOP
CONDITION
AI00587
CLOCK PULSE FOR
ACKNOWLEDGEMENT
89
LSB
AI00601
11/33

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